臺灣博碩士論文加值系統

巴特勒矩陣在波束切換系統中扮演著舉足輕重的角色，然而走線過長，往往是巴特勒矩陣的致命傷，為了改進此缺點，本論文提出三種不同創新架構之CMOS巴特勒矩陣，預計可以縮小整體電路面積。晶片均採用TSMC CMOS 0.18μm製程來實現。
第一個電路為運用地層浮升技術之CMOS 4x4巴特勒矩陣，其架構採用地層浮升技術枝幹耦合器當作3 dB耦合器。單純地層浮升技術枝幹耦合器之量測結果在36.5~41.5 GHz頻帶內，反射損失大於10.5 dB，隔離度均大於14 dB，植入損失5 dB，相位誤差為-3.5°~-0.7°，功率平衡為1.4 dB以內。運用地層浮升技術之CMOS 4x4巴特勒矩陣電路，量測結果在36.5~40 GHz頻帶內，輸入埠的反射損失都大於8 dB，輸出埠的反射損失都大於11 dB，輸入埠的植入損失扣除理想損耗6 dB，約為5 dB。各路輸出端之相位差分別為-45°±8°(1R)、135°±10°(2L)、-135°±8°(2R)、45°±7°(1L)。
第二個電路為CMOS 4x8非對稱式巴特勒矩陣此非對稱式架構利用輸入埠及空間中波束鏡像對稱性質，內嵌4個單刀雙擲開關(SPDT)去切換訊號路徑，在不改變波束特性前提下使輸入埠數量減半。相較傳統8x8巴特勒矩陣，可減少4組耦合器。量測結果在37~39 GHz頻帶內，輸入埠與輸出埠反射損失都大於15.2 dB，各路輸出埠之相位差分別為-157.5°±14.6°(4R)、22.5°±12.7°(1L)、-67.5°±21.5°(2R)、112.5°±30.2°(3L)、157.5°±15.1°(4L)、-22.5°±16.7°(1R)、67.5°±23°(2L)、-112.5°±21°(3R)。
第三個電路為CMOS無需交叉跨線及相移器之4x4巴特勒矩陣，本電路減少交叉跨線及相移器的使用，整體面積會比傳統4x4巴特勒矩陣小。量測結果在57~63 GHz頻帶內，輸入埠的反射損失都大於10 dB，輸出埠的反射損失都大於10.4 dB，輸入埠的植入損失扣除理想損耗6 dB，為1.8~3.3 dB。各路輸出埠之相位差分別為-45°±10°(1R)、135°±6°(2L)、-135°±8°(2R)、45°±7°(1L)。

Butler Matrix plays an essential role in beamforming array systems. However, it becomes more challenging due to the large chip area when the circuit is designed using CMOS process. In order to overcome this issue, this thesis proposes three different configurations for CMOS Butler Matrix designs. All circuits are fabricated using a TSMC 0.18μm process.
The first circuit is a 38-GHz CMOS 4x4 Butler matrix using raised ground plane technology. The so-called raised ground plane technology can easily achieve low impedance without occupying a large chip area. By applying this technology in a 4x4 Butler matrix design, the measurements show that the return losses are better than 8 dB, and better than 11 dB at output ports. The insertion loss is about 5dB excluding theoretically distributed loss of 6 dB. The phase difference are -45°±8°(1R), 135°±10°(2L), -135°±8°(2R), 45°±7°(1L) within 36.5~40 GHz.
The second circuit is a 38-GHz 4x8 asymmetric Butler Matrix. By taking the advantages on the mirror symmetry from a conventional Butler Matrix, four single-pole double-throw switches can be embedded to eliminate four input ports, consequently saving the areas of four couplers, four phase shifters, and crossovers. Measurement results show that the return losses at both input and output ports are better than 15.2 dB. The phase differences for those eight beam cases are -157.5°±14.6°(4R), 22.5°±12.7°(1L), -67.5°±21.5°(2R), 112.5°±30.2°(3L), 157.5°±15.1°(4L), -22.5°±16.7°(1R), 67.5°±23°(2L), -112.5°±21°(3R) within 37~39 GHz.
The third circuit is a 60-GHz 4x4 Butler Matrix without crossovers and phase shifters. This purpose of this design is to eliminate the use of crossovers and phase shifters so that the overall circuit size can be reduced. Measurement results show that the input port return loss is better than 10 dB, output port return loss is better than 10.4 dB, input port insertion loss deducting ideal loss 6 dB, is about 1.8~3.3 dB. output phase difference are -45°±10°(1R), 135°±6°(2L), -135°±8°(2R), 45°±7°(1L) within 57~63 GHz.

摘要 i
Abstract iii
目錄 v
圖目錄 vii
表目錄 xi
第一章 序論 1
1.1研究背景與動機 1
1.2巴特勒矩陣晶片之文獻探討 2
1.3論文架構與貢獻 5
第二章 運用地層浮升架構之CMOS 4x4巴特勒矩陣之設計 6
2.1 地層浮升技術簡介 6
2.2 CMOS運用地層浮升架構枝幹耦合器設計 9
2.2.1 CMOS運用地層浮升架構枝幹耦合器佈局與量測考量 14
2.2.2 CMOS運用地層浮升架構枝幹耦合器模擬與量測結果 15
2.3 CMOS運用地層浮升架構之4x4巴特勒矩陣設計 17
2.3.1 CMOS運用地層浮升架構之4x4巴特勒矩陣佈局與量測考量 22
2.3.2 CMOS運用地層浮升架構之4x4巴特勒矩陣模擬與量測結果 24
2.4 文獻比較 29
第三章 CMOS非對稱式巴特勒矩陣之設計 30
3.1簡介 30
3.2 晶片子電路設計 32
3.2.1寬邊帶耦合器設計 32
3.2.2單刀雙擲開關設計 34
3.2.3相移器及交叉跨線設計 36
3.3 CMOS非對稱式巴特勒矩陣佈局與量測考量 37
3.4 CMOS非對稱式巴特勒矩陣模擬與量測結果 40
3.5 文獻比較 51
第四章 CMOS無需交叉跨線及相移器之4x4巴特勒矩陣設計 52
4.1 簡介 52
4.2 傳統90°耦合器理論分析及設計 53
4.3 特性改變之耦合器設計 57
4.4 CMOS無需交叉跨線及相移器之4x4巴特勒矩陣佈局與量測考量 60
4.5 CMOS無需交叉跨線及相移器之4x4巴特勒矩陣模擬結果與量測結果 61
4.6 文獻比較 66
第五章 結論與展望 67
參考文獻 69

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