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研究生:蔡昀廷
研究生(外文):TSAI, YUN-TING
論文名稱:下行鏈路功率域非正交多重存取收發機系統之模擬與硬體實現
論文名稱(外文):Simulation and Hardware Implementation for the Downlink Power-Domain Non-Orthogonal Multiple Access System
指導教授:劉宗憲劉宗憲引用關係
指導教授(外文):LIU, TSUNG-HSIEN
口試委員:吳文榕陳喬恩劉宗憲賴癸江朱元三
口試日期:2019-07-19
學位類別:碩士
校院名稱:國立中正大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:72
中文關鍵詞:非正交多重存取正交分頻多工連續干擾消除疊加編碼
外文關鍵詞:NOMAOFDMSICSC
相關次數:
  • 被引用被引用:1
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  • 下載下載:11
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在通訊系統中,隨著用戶數和傳輸量的提高,頻寬(bandwidth)的運用和頻譜效益(spectrum efficiency)是相當重要的問題。與分頻多工( Frequency Division Multiple Access, FDMA)、分時多工(Time Division Multiple Access, TDMA)、分碼多工(Code Division Multiple Access, CDMA)、正交分頻多工(Orthogonal Frequency Division Multiple Access, OFDMA )多重存取技術相比,非正交多重存取(Non-Orthogonal Multiple Access, NOMA)技術使多個用戶能在單一Resource Block (Time/Frequency)下共享無線資源,增加頻譜效率和吞吐量(throughput)。然而用戶在共享無線資源的情況下會造成用戶端之間的互相干擾。在許多的NOMA技術中,本文深入淺出的探討Power-Domain NOMA技術,考慮兩個用戶的場景,利用在傳送端將離基地台遠近不同的強用戶(strong user)和弱用戶(weak user)作功率(power)分配並疊加(superpose),且在接收端使用連續干擾消除(Sucessive Interference Cancellation, SIC) 檢測用戶訊號。再以Malab模擬雙用戶在不同功率分配和調變(modulation)技術之結果,再以Simulink設計Model並使用HDL Coder轉換實際以FPGA進行硬體快速實現,並使用TSMC 90nm CMOS製程進行ASIC電路合成。
The bandwidth and spectrum efficiency in wireless communication are related to the number of users and the data rate of each user. Compared to the frequency division multiple access (FDMA), time division multiple access (TDMA), code division multiple access (CDMA), orthogonal frequency division (OFDMA), the new non-orthogonal multiple access (NOMA) technology enables multiple users to share wireless resources in a single time/frequency resource block to increase spectrum efficiency and data throughput. However, when multiple users share the same wireless resources, they cause mutual interference to one another. Among the many NOMA schemes, the simple power-domain NOMA technology is explored in this thesis. A scenario of two users is considered. At the transmitter side, superposition coding (SC) of signals for two users is applied. One strong user is located at the cell center, and, the other weak user is located at the cell edge. At the receiver side, successive interference cancellation (SIC) is applied to detect the users. Simulation results for the two users with different power allocation and modulation schemes are reported. The transmitter and receiver for the NOMA technique are designed under the Simulink environment. The designed Simulink model is converted by the HDL coder. The generated HDL code is download to the Zedboard FPGA for hardware simulation. Finally, the HDL code is also synthesized by TSMC 90 nm CMOS technology.
目錄
1 簡介 1
1.1 前言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 研究動機 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 內容大綱 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 多重存取技術介紹 (Introduction of Multiple Access) 3
2.1 正交多重存取 (Orthogonal Multiple Access, OMA) . . . . . . . . . . . 3
2.2 非正交多重存取 (Non-Orthogonal Multiple Access, NOMA) . . . . . . 7
3 正交分頻多工 (Orthogonal Frequency Division Multiplexing, OFDM) 10
3.1 多載波通訊系統 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 保護區間 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 通道模型 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 功率域非正交多重存取 (Power-Domain Non-Orthogonal Multiple Access) 20
4.1 疊加編碼 (Superposition Coding) . . . . . . . . . . . . . . . . . . . . . 21
4.2 連續干擾消除解調法 (Successive Interference Cancellation, SIC) . . . . 22
4.2.1 Symbol Level SIC 與 Codeword Level SIC . . . . . . . . . . . 25
4.2.2 最佳 α 值的設計 . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 PD-NOMA 與 OMA 系統之性能比較 . . . . . . . . . . . . . . . . . . . 28
4.4 OFDM based NOMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Simulink HDL Coder and FPGA 35
5.1 Simulink Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 HDL Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6 模擬結果及合成數據 (Simulation and Implementation) 42
6.1 Matlab 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2 Simulink 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 Result of HDL Coder and FPGA-in-the-Loop . . . . . . . . . . . . . . 58
6.4 ASIC 合成結果報告 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7 結論 63
8 特別感謝 63
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