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研究生:楊欣靜
研究生(外文):YANG, HSIN-CHING
論文名稱:適用於預處理輔助空間調變的 一位元預編碼器設計研究
論文名稱(外文):A Research on One-Bit Precoder Design for Precoding-Aided Spatial Modulation
指導教授:陳喬恩
指導教授(外文):CHEN,CHIAO-EN
口試委員:黃元豪蔡佩芸邱茂青劉宗憲
口試委員(外文):HUANG, YUAN-HAOTSAI, PEI-YUNCHIU, MAO-CHINGLIU, TSUNG-HSIEN
口試日期:2019-07-17
學位類別:碩士
校院名稱:國立中正大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:60
中文關鍵詞:預處理輔助空間調變一位元預編碼器
外文關鍵詞:Precoding-aided spatial modulationone bit precoder
相關次數:
  • 被引用被引用:0
  • 點閱點閱:100
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  • 收藏至我的研究室書目清單書目收藏:0
在這篇論文中,我們探討一個適用於預處理輔助空間調變(Precoding-aided
spatial modulation, PSM) 的多輸入多輸出系統(Multiple-input multiple-output)
一位元預編碼器設計。現有的預處理輔助空間調變系統下的預編碼器,例如最
小均方差(Minimum mean square error, MMSE) 預編碼器與迫零(Zero Forcing,
ZF) 預編碼器皆須使用高解析度的數位/類比轉換器(Digital-to-analog converters,
DAC),其中DAC 的功率消耗隨解析度成指數增長。當傳送端配備大量天線時,
這將導致高的硬體複雜度以及過多的電路功率消耗。為了解決這個問題,可以
在傳送端使用one-bit DAC 以降低傳送端在硬體實現上的功率消耗成本及複雜
度,如此可以看出一位元預編碼在巨量多輸入多輸出系統(Massive multiple-input
multiple-output) 應用上的優點。本篇論文的目標是提出一種基於預處理輔助空間
調變系統的一位元預編碼器設計。我們使用電腦模擬以比較使用MMSE 預編碼
器,ZF 預編碼器以及一位元預編碼器在預處理輔助空間調變系統下的位元錯誤率
性能。
Precoders in existing precoding-aided spatial modulation (PSM) multiple-input
multiple-output (MIMO) systems, such as minimum mean square error (MMSE)
precoder and zero forcing (ZF) precoder, are often equipped with high-resolution
DACs. As the power consumption of DACs grow exponentially with the resolution,
high hardware complexity and excessive circuit power consumption is required in
conventional design. In order to address this issue, we propose to design the precoder
of a PSM-MIMO system facilitating the use of 1-bit DACs at the transmitter. In
this thesis, we propose two precoder designs for PSM-MIMO system under 1-bit
DAC hardware constraints. Finally, numerical simulations ar performed to verify
the bit error rate performance of our proposed one-bit precoders.
1 序論1
1.1 研究動機與目的. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 章節概要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 一位元預編碼器背景介紹4
2.1 一位元預編碼器簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 一位元預編碼器下的系統模型. . . . . . . . . . . . . . . . . . . . . . 7
2.3 參考文獻[14] 中一位元預編碼器設計. . . . . . . . . . . . . . . . . . 9
2.3.1 推導定理1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 參考文獻[2] 所提出之高SNR 下一位元預編碼器設計. . . . . . . . 17
3 預處理輔助空間調變系統介紹22
3.1 預處理輔助空間調變系統簡介. . . . . . . . . . . . . . . . . . . . . . 22
3.2 預處理輔助空間調變系統的系統模型. . . . . . . . . . . . . . . . . . 25
3.3 在嚴格單天線功率限制下的預編碼器研究. . . . . . . . . . . . . . . 27
3.3.1 MMSE 預編碼器設計. . . . . . . . . . . . . . . . . . . . . . 28
3.3.2 ZF 預編碼器設計. . . . . . . . . . . . . . . . . . . . . . . . . 29
4 本論文提出之在預處理輔助空間調變下的一位元預編碼器設計研究30
4.1 一位元預編碼器結合預處理輔助空間調變下的系統模型. . . . . . . 30
iii
4.2 問題描述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3 使用DR-splitting 方法之預編碼器設計. . . . . . . . . . . . . . . . . 33
4.3.1 Alternating Direction Method of Multipliers . . . . . . . . . . 37
4.4 在高SNR 下使用BCR 方法之預編碼器設計. . . . . . . . . . . . . 38
4.4.1 Biconvex Relaxation . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.2 交替最佳化. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 電腦模擬45
6 結論49
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
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