臺灣博碩士論文加值系統

複晶矽薄膜電晶體的特性擁有較高的場效應遷移率與驅動電流，在各方面如記憶元件、太陽能電池、主動式液晶顯示器等，都已經被廣泛使用於其中。傳統的複晶矽薄膜電晶體的特性已經不足以應付，所以提升其薄膜電晶體的效能，成為現今重要的課題。
從之前發表的論文中得知雙通道結構能使元件有效的提升複晶矽薄膜電晶體的驅動電流，雖然高性能的雙通道複晶矽薄膜電晶體能夠有效的降低漏電流，但有相當大的寄生電阻產生。所以我們提出了以雙通道結構嘗試不同結構來降低複晶矽薄膜電晶體的寄生電阻並增加驅動電流。
本研究中，我們提出了新式雙通道結合抬升式源汲極(RSD)與汲極輕摻雜(LDD)複晶矽薄膜電晶體(DCLDD-TFT)，且此結構藉由加入抬升式汲源極結構(Raised Source/Drain, RSD)已得到較好的元件特性與較高的導通電流，不同厚度的氧化層及通道厚度能夠互相比較得到較低的漏電流和開關電流比。從模擬結果中得知，與傳統型的元件相比，新的設計擁有較低的電流密度及電場，且能有效降低漏電流，以改善其不理想效應。
關鍵詞：ISE-TCAD、薄膜電晶體、輕摻雜汲極、抬昇式汲源極、雙通道結構

The complex crystalline silicon thin film transistor has been developed in many aspects such as storage element, solar cell, active liquid crystal display and so on due to its high field effect mobility and driving current. However, the traditional complex crystalline silicon thin film transistor has the characteristics are not enough to copy with the new type of electronic products.
Although the high-performance double-channel complex crystalline silicon thin film transistor can effectively reduce the leakage current, It has a considerable parasitic resistance generation. So we propose a dual-channel structure combined with different light doping to reduce the parasitic resistance of the polycrystalline silicon thin film transistor and increase the driving current.
In this study, we propose a different thicknesses of oxide layer and channel thickness can be compared with each other to obtain lower leakage current and switching current ratio. It is known from the simulation results that the new design has lower current density and electric field than the conventional components, which can effectively reduce leakage current to improve the undesired effects of components.
Keyword：Integrated System Engineering (ISE-TCAD), Thin-film transistors (TFTs), Different Light Doped Drain (DLDD), Raised source and drain (RSD), Double Channel (DC)

誌謝 3
摘要 4
圖目錄 8
第一章 介紹 10
1.1 薄膜電晶體簡介與應用 10
1.2 複晶矽薄膜電晶體之關鍵製造技術 11
1.2.1 固相結晶 (Soild Phase Crystallization, SPC) 13
1.2.2 金屬感應再結晶 (Metal-Induced Crystallization, MIC) 13
1.2.3 準分子雷射退火 (Excimer Laser Annealing, ELA) 14
1.3 薄膜電晶體之不理想效應 15
1.3.1 漏電流效應 16
1.3.2 熱載子效應 19
1.3.3 扭結效應 22
1.4 薄膜電晶體之基本元件結構 25
1.4.1 Offset 結構 25
1.4.2 LDD (Light Doped Drain) 結構 26
1.4.3 RSD (Raised Source/Drain) 結構 27
1.4.4 GOLDD (Gate-overlapped Lightly Doped Drain) 結構 28
1.4.5 FID (Field Induced-Drain) 結構 28
1.5 研究動機 29
1.6 研究架構 31
第二章 文獻回顧與結構設計 31
2.1結構之文獻回顧 31
2.1.1 Bottom Gate Poly-Si TFT with LDD 31
2.1.2 Double Channel Poly-Si TFT With RSD 33
2.2新提出之雙通道之不同結構薄膜電晶體(DCDLDD-TFT) 35
第三章DCLDD-TFT之模擬製程 37
3.1元件製程結構 37
3.2元件製程模擬流程 37
3.2.1元件光罩定義 37
3.2.2元件製程流程 40
第四章 不同結構之模擬與分析 48
4.1新式薄膜電晶體模擬與分析 48
4.2雙通道薄膜電晶體之不同底部氧化層厚度分析 48
4.2.1不同氧化層厚度之模擬圖比較 49
4.2.2不同氧化層厚度之折線圖比較 50
4.3雙通道薄膜電晶體之不同頂部通道厚度特性分析 54
4.3.1不同頂部通道厚度之模擬圖比較 55
4.3.2不同頂部通道厚度之折線圖比較 58
第五章 改良DC-TFT之特性模擬與分析 61
5.1電場模擬與分析 61
5.1.1底部通道之電場分析 62
5.2電流密度模擬與分析 63
5.2.1底部通道之電場分析 64
5.3離子碰撞模擬與分析 66
5.3.1底部通道之離子碰撞分析 67
第六章結論 70
參考文獻 72

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