功率損耗一直是人類不斷探索的問題，尤其是在這講求高性能的時代。其中，如何降低電子產品的功率損耗是很重要的議題。在功率元件(Power Device)上，改善功率損耗，也是開發者們共同的目標。近年開發出一新型結構「溝槽分離式閘極金氧半場效電晶體(Split-Gate MOSFET)」，其元件改善了功率損耗以及可在高頻環境下工作。本論文利用SILVACO模擬軟體，模擬耐壓100伏的Split-Gate MOSFET功率元件，分析其元件特性，接著以降低元件特徵導通電阻為目的，對Split-Gate MOSFET進行元件優化，於優化過成中，前段所進行的是元件的尺寸微縮，利用元件尺寸的微縮降低元件的特徵導通電阻，而後半段進行的是改變元件的結構，提出「多重分離閘極溝槽式金氧半場效電晶體(Multi-Split-Gate)」，含2個Split-Gate，4個Split-Gate與6個Split-Gate。其中以4個Split-Gate 結構的元件特性較佳，所以再以此結構進行微縮元件尺寸的優化。經一系列優化過程後，Cell pitch為2.5 um的Split-Gate結構到新結構Cell pitch為2.0 um的Multiple Split-Gate 4，特徵導通電阻降低約55%的佳績，大幅降低了元件功率損耗，提升元件效能。

The power loss has always been a problem that humans continue to explore, especially in this high-performance era. In which how to reduce the power loss of electronic products is an important issue. Improving power loss on power devices is a common goal for developers. In recent years, a new structure, called "Split-Gate Metal Oxide Semiconductor Field Effect Transistor (Split-Gate MOSFET)", has been developed, which power loss has been improved, and can be operated in high frequency environments. In this thesis, SILVACO simulation software was used to simulate a 100-volt Split-Gate MOSFET and to study its characteristics. The Split-Gate MOSFETs were optimized by simulation for the purpose of reducing their on-resistance. First the size of the Split-Gate MOSFET was scaled. The purpose is to reduce the specific on-resistance (Ron,sp). Finally, we changed the structure of the device and proposed the Multi-Split-Gate MOSFET including 2 Split-Gate, 4 Split-Gate and 6 Split-Gate. The characteristics of 4 Split-Gate is better than others. Therefore, this structure had been further optimized for the miniature size finally. After a series optimization, compared with 2.5 um cell pitch Split-Gate, Ron,sp had reduced about 55% for new structure with 2.0 um cell pitch and 4 Split-Gate in this paper.

致謝.....................................................................I
摘要....................................................................II
Abstract...............................................................III
目錄....................................................................IV
表錄....................................................................VI
圖錄...................................................................VII
第一章 序論..............................................................1
前言.....................................................................1
研究動機.................................................................1
論文架構.................................................................2
第二章 Power MOSFET 操作原理..............................................3
2-1 導通與耐壓機制........................................................3
2-2 崩潰機制.............................................................5
2-3 Split-Gate MOSFET 介紹...............................................6
2-4 Split-Gate MOSFET基本結構與操作原理...................................7
2-5 Split-Gate MOSFET文獻回顧............................................8
2-6 總結.................................................................9
第三章 元件模擬..........................................................18
3-1 磊晶層阻值模擬.......................................................19
3-2 T-Gate MOSFET與Split-Gate MOSFET溝槽深度模擬.........................20
3-3 T-Gate MOSFET與Split-Gate MOSFET耐壓氧化層(Bottom Oxide)厚度模擬.....21
3-4 Trench-Gate、T-Gate與Split-Gate元件寄生電容模擬......................22
3-5 總結................................................................24
第四章 Split-Gate MOSFET優化模擬與Multi-Split-Gate MOSFET................35
4-1 Split-Gate MOSFET微縮元件尺寸優化....................................36
4-2 Multi-Split-Gate結構介紹與模擬分析...................................38
4-3 Multi-Split-Gate 4微縮元件尺寸優化...................................43
4-4 總結................................................................43
第五章 未來展望..........................................................60
參考文獻.................................................................61

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