臺灣博碩士論文加值系統

本篇論文主要研究在單端輸入之連續逼近式類比數位轉換器之三維電容佈局架構，相較於以往的連續逼近式類比數位轉換器所使用的電容架構來比較電容面積時，約可降低10~20%的面積，並可達到基本電路需求。

新的電容架構首先可降低10~20%的面積外，因不需再增加製程光罩，所以並不會增加晶圓成本，即表示可藉此有效降低晶片成本並提升毛利率。

在此採用UMC80nm 1P5M 1.2V_6V_32V製程，除了進行10bit單端輸入連續逼近式類比數位轉換器的電路設計外，也增加電容陣列測試單位來量測電容陣列是否符合本身設計之規格。

在最後量測結果部份，當取樣頻率為 5MHz、輸入頻率為101kHz時，所獲得之 ENOB 為 8.98 bit ；當取樣頻率為 2.5 MHz、輸入頻率為101kHz時，所獲得之 ENOB 為 8.81 bit；而金屬-氧化層-金屬交錯型電容陣列在量測上誤差值落在 10 % 以內，也符合一般製程變異的範圍裡。

This thesis mainly studies the three-dimensional capacitor layout architecture for a single-ended input Successive Approximation Analog-to-Digital Converter (SAR ADC). Compared with the capacitance architecture used in the conventional SAR ADCs, the area of the proposed device can be reduced by about 10-20% and can meet the basic circuit requirements.

The proposed capacitor architecture can be reduced by 10-20% first. Since there is no need to increase the process mask, it will not increase the wafer cost, which means that the cost of the wafer can be effectively reduced and the gross profit margin can be improved.

In this case, the UMC80nm 1P5M 1.2V_6V_32V process is used. In addition to the circuit design of the 10-bit single-ended input SAR ADC, the tested unit of capacitor array is also added to measure whether the capacitor array meets the specifications of its own design.

For measurement, when the sampling frequency is 5 MHz and the input frequency is 101 kHz, the obtained ENOB is 8.98 bit. When the sampling frequency is 2.5 MHz and the input frequency is 101 kHz, the obtained ENOB is 8.81 bit. The metal-oxide-metal staggered capacitor array has a difference of less than 10% in measurement, which is also in the range of general process variation.

摘要 i
Abstract ii
目錄 iii
表目錄 v
圖目錄 vi
第一章 簡介 1
1.1研究動機 1
1.2論文大綱 2
第二章 類比數位轉換器的基本原理 3
2.1類比數位轉換器介紹 3
2.2類比數位轉換器之特性參數 4
第三章 電容種類與佈局方式之探討與定義 10
3.1連續逼近式類比數位轉換器之架構 10
3.2電容種類之分析 11
3.3金屬-氧化層-金屬電容容值計算 12
3.4電容陣列佈局影響性 16
3.5金屬-氧化層-金屬電容容值需求分析 18
第四章 單端輸入連續逼近式類比數位轉換器之電路架構分析與實現 20
4.1連續逼近式類比數位轉換器之架構 20
4.2運用靴帶式開關之取樣保持電路 23
4.3動態栓鎖比較器 25
4.4內部的時脈產生電路 27
4.5切換電容開關的DAC控制電路 28
4.6佈局圖 29
4.7電路後模擬數據 33
第五章 晶片量測 35
5.1量測環境 35
5.2 PCB 板製作 36
5.3電容量測結果 38
5.4晶片量測結果 39
5.5晶片照相圖 41
第六章 結論與未來研究之方向 44
參考文獻 45

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