[1]G. E. Moore, Cramming More Components Onto Integrated Circuits, Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, 1998, doi: 10.1109/JPROC.1998.658762.
[2]M. Kanellos. (2003, February 11) Moore's Law to roll on for another decade. CNET. Available: https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/
[3]C. C. Hu, MOSFETs in ICs-Scaling, Leakage, and Other Topics, in Modern Semiconductor Devices for Integrated Circuits, 2009, pp. 259-289.
[4]2003 ITRS EMERGING RESEARCH DEVICES (ERD2003.pdf). International Technology Roadmap for Semiconductors (ITRS). https://www.dropbox.com/sh/0ce36nq4118wiag/AACZ1MVxbt8GBSPlla7-FoMda?dl=0&preview=ERD2003.pdf (accessed.
[5]賴威廷, 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析, 碩士, 電機工程研究所, 國立中央大學, 桃園縣, 2005. [Online]. Available: https://hdl.handle.net/11296/q6w3rp[6] S. D. Franceschi et al., SOI technology for quantum information processing, in 2016 IEEE International Electron Devices Meeting (IEDM), 3-7 Dec. 2016 2016, pp. 13.4.1-13.4.4, doi: 10.1109/IEDM.2016.7838409.
[7] L. Hutin et al., All-Electrical Control of a Hybrid Electron Spin/Valley Quantum Bit in SOI CMOS Technology, in 2018 IEEE Symposium on VLSI Technology, 18-22 June 2018 2018, pp. 125-126, doi: 10.1109/VLSIT.2018.8510665.
[8]H. Aminzadeh, M. A. Dashti, and M. Miralaei, Nano-Scale Silicon Quantum Dot-Based Single-Electron Transistors and Their Application to Design of Analog-to-Digital Convertors at Room Temperature, Journal of Circuits, Systems and Computers, vol. 26, no. 12, 2017, doi: 10.1142/s0218126617502012.
[9]D. V. Averin and K. K. Likharev, Coulomb blockade of single-electron tunneling, and coherent oscillations in small tunnel junctions, Journal of Low Temperature Physics, vol. 62, no. 3, pp. 345-373, 1986/02/01 1986, doi: 10.1007/BF00683469.
[10]D. A. Neamen, SEMICONDUCTOR PHYSICS & DEVICES: BASIC PRINCIPLES, Fourth ed. Americas, New York: McGraw-Hill, 2012.
[11]P. Harrison and A. Valavanis, Quantum wells, wires and dots : theoretical and computational physics of semiconductor nanostructures, Fourth ed. United Kingdom: John Wiley & Sons, 2016.
[12]何繼勛, Single-Electron Transistors, 電子與材料, no. 13, 2002.
[13]M. Miralaie, M. Leilaeioun, and K. Abbasian, Modeling of a Room-Temperature Silicon Quantum Dot-Based Single-Electron Transistor and the Effect of Energy-Level Broadening on Its Performance, Journal of Electronic Materials, vol. 42, no. 1, pp. 47-57, 2012, doi: 10.1007/s11664-012-2315-z.
[14]M. Miralaie and A. Mir, Performance analysis of single-electron transistor at room-temperature for periodic symmetric functions operation, The Journal of Engineering, vol. 2016, no. 10, pp. 352-356, 2016, doi: 10.1049/joe.2016.0139.
[15]C. Wasshuber, Computational Single-Electronics. New York: Springer-Verlag Wien, 2001.
[16]S. Mahapatra and A. M. Ionescu, Hybrid CMOS Single-Electron-Transistor Device and Circuit Design. Artech House, 2006.
[17]K. K. Likharev, Single-electron devices and their applications, Proceedings of the IEEE, vol. 87, no. 4, pp. 606-632, 1999, doi: 10.1109/5.752518.
[18]S. S. Dan and S. Mahapatra, Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits, IEEE Transactions on Nanotechnology, vol. 9, no. 1, pp. 38-45, 2010, doi: 10.1109/tnano.2009.2022833.
[19]S. Datta, Quantum Transport Atom To Transistor. Cambridge, U.K.: Cambridge University Press, 2005.
[20]Z. A. K. Durrani, Single-Electron Devices and Circuits in Silicon (Single-Electron Devices and Circuits in Silicon).
[21]S. J. Shin et al., Si-based ultrasmall multiswitching single-electron transistor operating at room-temperature, Applied Physics Letters, vol. 97, no. 10, 2010, doi: 10.1063/1.3483618.
[22]S. J. Shin et al., Room-temperature charge stability modulated by quantum effects in a nanoscale silicon island, Nano Lett, vol. 11, no. 4, pp. 1591-7, Apr 13 2011, doi: 10.1021/nl1044692.
[23]N. H. E. Weste and D. M. Harris, CMOS VLSI Design - A Circuits and Systems Perspective, Fourth ed. United States of America: Pearson Education, 2010.
[24]C. Sathe, S. S. Dan, and S. Mahapatra, Assessment of SET Logic Robustness Through Noise Margin Modeling, IEEE Transactions on Electron Devices, vol. 55, no. 3, pp. 909-915, 2008, doi: 10.1109/ted.2007.915086.