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研究生:薛柏安
研究生(外文):Shiue, Po-An
論文名稱:模擬塊材與絕緣層上矽鰭式場效電晶體之本質參數變異研究
論文名稱(外文):Threshold Voltage Variability due to Random Variability Sources in Bulk and SOI FinFETs
指導教授:陳明哲陳明哲引用關係
指導教授(外文):Chen, Ming-Jer
口試委員:陳明哲林大文游國豐楊國男
口試委員(外文):Chen, Ming-JerLin, Da-WenYu, Kuo-FengYang, Kuo-Nan
口試日期:2018-10-19
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:107
語文別:英文
論文頁數:70
中文關鍵詞:臨界電壓變異性鰭狀電晶體絕緣層上矽塊材
外文關鍵詞:VariabilityFinFETSOIBulk
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隨著鰭狀場效電晶體不斷微縮,臨界電壓的擾動也變的越來越重要,而造成擾動的三種主要本質參數差異分別為: 隨機參雜濃度擾動 (RDF)、線邊緣的粗糙程度 (LER) 以及金屬閘極顆粒度 (MGG)。這些現象會造成奈米及半導體元件之臨界電壓擾動進而劣化整體元件之性能及良率。在這次本質參數差異模擬過程中,對於LER效應我們使用修正過的預測模型至於RDF和MGG則使用TCAD內建的方法sIFM以節省模擬時間並同時將樣本數提升到20000以減少樣本數不足引起的誤差。如此一來就能在有限的時間內探討不同施加偏壓(VD) 、結構參數 (LG、Wfin、Hfin、EOT、angle) 、不同擴散程度以及本質參數的三種設想 (悲觀、一般、樂觀) 各自對本質參數變異的影響。經由模擬結果可以得知:
SOI FinFETs能大幅抑制LER效應,這是由於經歷比較少道製程導致RMS大約只有Bulk FinFETs的一半。LER的參數對σVT影響程度由大到小依序為RMS,cross-correlation factor 最後才是correlation length 。然而correlation length卻會嚴重影響weight分布的集中程度。
另外LG, Wfin, Hfin, EOT and angle這五種結構參數在VD = 0.05 V 時σVT.LER最嚴重是發生在Wfin = 5 nm。不過額外增加一度的angle可降低至60%的σVT.LER,由此可知在Wfin小的情況下增加angle可能會是克服LER的方法之一。另一方面在VD = 0.7 V時則因為短通道效應的緣故,最嚴重的情形轉而發生在LG = 14 nm。這也告訴了我們對於σVT.LER,極小尺度元件在LG, Wfin和angle之間的取捨將變得相當重要。RDF則因為通道無參雜的緣故,只有在電性極差 (LG = 14 nm, Wfin = 9 nm以及angle ≥ 3 degree) 或者是擴散嚴重 (DG ≥ 6.6 nm/dec) 的情形下才略有影響。對於MGG效應, (LG、Wfin、Hfin、angle) 都會隨著縮小而導致σVT.MGG更嚴重,我們可以用RGG (= AGS/(Weff LG)0.5) 將參數歸納成一個經驗公式並且斜率大意味著微縮所造成的額外σVT.MGG將更大。而σVT.MGG可以藉由提升製程技術進而縮小AGS或是集中金屬閘極不同顆粒方向的比例來達到抑制的效果。此外,隨著擴散程度上升, σVT.RDF 和 σVT.MGG上升,然而σVT.LER則有下降的趨勢。
As FinFETs continues to scale down, VT variations become more and more important. There are three major variability sources: Random Dopant Fluctuation (RDF), Line Edge Roughness (LER) and Metal Gate Granularity (MGG). These effects will cause VT fluctuation and hence deteriorate devices performance and yield. In this study, LER-induced VT predictive model is adopted and statistical impedance field method (sIFM) is used to simulate RDF and MGG. Furthermore, we increase the sample size to 20000 so as to eliminate error caused by insufficient samples. Therefore, we can simulate σVT in various conditions such as drain bias (VD), structure parameters (LG, Wfin, Hfin, EOT and angle), diffusion gradient (DG) and three scenarios (pessimistic, normal and optimistic) in a short time. From the simulation results we can know that:
SOI FinFETs can suffer much less LER than Bulk FinFETs due to only half of RMS by less process steps. Comparing each LER parameters, RMS, cross-correlation factor and then correlation length are in descending order of impacts on σVT. However, correlation length will influence weight function distribution seriously.
Besides, among LG, Wfin, Hfin, EOT and angle, σVT.LER will be largest for Wfin = 5 nm at VD = 0.05 V while additional 1 degree will decrease σVT.LER to 60%, indicating that adding degrees for small Wfin may be one of the solutions to suppress LER effect. On the other hand, largest σVT at VD = 0.7 V turns out to be at LG = 14 nm because serious short channel effect will enhance DIBL and cause extra σVT.LER. To control σVT.LER, it is obvious that the trade-off between LG, Wfin and angle will become extremely important in nano-scale device. For RDF effect, only worse electric integrity cases (LG = 14 nm, Wfin = 9 nm and angle ≥ 3 degree) and large diffusion gradient cases (DG ≥ 6.6 nm/dec) have impacts on σVT.RDF but still quite low compared to LER and MGG. For MGG effect, σVT.MGG will increase as LG, Wfin, Hfin and angle scale down, which can be concluded to an empirical formula by merging these parameters to RGG (= AGS/(WeffLG)0.5). The larger slope of σVT.MGG over RGG means it will cost more extra σVT.MGG to scale down. To suppress σVT.MGG, one can either control process conditions to reach a smaller AGS or higher probability of preferred-oriented grains. In addition, as diffusion gradient increases, σVT.RDF and σVT.MGG increase while σVT.LER decreases.
摘要 I
Abstract III
Acknowledgement V
Chapter 1 Introduction 1
Chapter 2 Comparative study in Bulk and SOI 4
2.1 Introduction 4
2.2 Device Simulation setting and Calibration 4
2.3 Systematic Sources of Variation 6
Chapter 3 Threshold Voltage Variability Induced by Line Edge Roughness 9
3.1 Introduction 9
3.2 Methodology 9
3.3 Results and Discussions 13
Chapter 4 Random Dopant Fluction and Metal Grain Granularity 16
4.1 Introduction 16
4.2 Methodology 17
4.3 Results and Discussions 17
Chapter 5 Conclusion 19
References 21
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