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研究生:管金儀
研究生(外文):Kuan, Chin-I
論文名稱:氮氧化鋅薄膜研製與電晶體應用之研究
論文名稱(外文):Study on the Preparation and Device Applications of Zinc Oxynitride Films
指導教授:林鴻志林鴻志引用關係黃調元黃調元引用關係
指導教授(外文):Lin, Horng-ChihHuang, Tiao-Yuan
口試委員:林鴻志李佩雯莊紹勳趙天生張鼎張王水進張廖貴術
口試委員(外文):Lin, Horng-ChihLi, Pei-WenChung, Shao-ShiunChao, Tien-ShengChang, Ting-ChangWang, Shui-JinnChang-Liao, Kuei-Shu
口試日期:2018-11-28
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:107
語文別:中文
論文頁數:256
中文關鍵詞:氧化物半導體薄膜電晶體氮氧化鋅氧化鋅氧化銦鎵鋅薄膜輪廓工法電子遷移率短通道源汲極電阻反向器電壓轉換曲線電壓增益穩定性
外文關鍵詞:oxide-semiconductorthin-film transistorZnONZnOIGZOfilm-profile engineeringmobilityshort channelsource/drain resistanceinvertersvoltage transfer curvesvoltage gainstability
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本篇論文中,我們成功地利用反應式磁控濺鍍系統,以鋅作為靶材並適當調變氬氣、氧氣、氮氣的比例,製備出高品質的N型氮氧化鋅(zinc oxynitride, ZnON)薄膜。同時搭配“薄膜輪廓工法” (film-profile engineering, FPE),製作並分析高效能次微米通道長度之氮氧化鋅薄膜電晶體(thin-film transistor, TFT)。接著應用此薄膜不易與鋁形成介面氧化層的特性,作為氧化鋅(zinc oxide, ZnO)和氧化銦鎵鋅(indium gallium zinc oxide, IGZO)薄膜電晶體,甚至反向器之接觸層,以改善電特性。
在薄膜沉積部分,我們探索了許多不同的沉積條件對於薄膜特性上的影響,並於最終成功地找出一適當的沉積方式製備高品質氮氧化鋅。基本上氮氧化鋅是非晶結構(amorphous phase),鋅、氧和氮三種元素均勻、雜散地分布其中。透過X射線光電子能譜(x-ray photoelectron spectroscopy)的分析,我們可以得知氮氧化鋅薄膜元素組成比例,鋅/氧/氮= 64/19/17 %。由於氮元素的摻入,使得氮氧化鋅有著遠較氧化鋅為窄的能隙(band gap)、低等效電子質量(effective electron mass)、高載子遷移率(carrier mobility)的特性。高達100 cm2/Vs的載子遷移率是氮氧化鋅最引人注目的優點。
於研究中,我們採用薄膜輪廓工法製作次微米線寬的氮氧化鋅薄膜電晶體。此方法的優點是僅需一次的微影製程即可製作出小線寬的元件,且所製作的次微米氮氧化鋅薄膜電晶體展現出良好的特性,包括55~60 cm2/Vs的場效電子遷移率(field-effect mobility)、約108的開關電流比(ION/IOFF),以及小於150 mV/dec的次臨界擺幅 (subthreshold swing)。同時我們也製作獨立金屬閘極的元件,可大幅抑制閘極漏電流,提高元件之開關電流比。另外薄膜輪廓工法搭配電子束微影(e-beam lithography)我們也可製作的65奈米氮氧化鋅元件表現出良好的電特性,例如108的開關電流比、8.3 cm2/Vs的電子遷移率。以上實驗成果說明了氮氧化鋅薄膜應用於短通道元件的莫大潛力。
吾人觀察到氮氧化鋅薄膜不易和氧化物半導體形成介面氧化層。基於此特性,我們提出將之應用於改善元件接觸電阻的構想。於氧化鋅和氧化銦鎵鋅薄膜電晶體的金屬和半導體間,加入一層約10奈米的氮氧化鋅接觸層,可有效抑制介面氧化層的形成,在元件電特性方面有著顯著的提升。同時藉由萃取源汲極電阻(source/drain resistance, RSD)、接面元素組成的方式,更進一步驗證接觸電阻與氧含量的降低對於元件特性的影響。除了單顆元件,氮氧化鋅接觸層亦可應用於邏輯閘電路。我們將之應用於由垂直堆疊的負載(load)及驅動(driver)電晶體所形成的空乏式(depletion-mode)反向器(inverter)。其電壓轉換曲線(voltage transfer curve)以及電壓增益(voltage gain)皆因氮氧化鋅接觸層的加入而有所提升。此外,氮氧化鋅接觸層經過長時間的存放也能維持相當高的穩定性。
In this dissertation, we have successfully prepared high-quality n-type zinc oxynitride (ZnON) films with reactive magnetron sputtering system by properly adjusting ratio of Ar, O2 and N2. We also fabricated and characterized high-performance sub-micron ZnON thin film transistors (TFTs) by using a novel “film-profile-engineering” (FPE) approach. Make a good use of the feature that ZnON can hardly form interfacial layer as capped by aluminum, the performance of TFTs and inverters with ZnO and IGZO channel can be improved.
The effects of various deposition recipes on film properties are studied. A fine recipe to deposit high-quality ZnON films is finally developed. Basically ZnON is amorphous in which Zn, O and N are distributed randomly and disorderly. With the analyses of x-ray photoelectron spectroscopy (XPS) we have learned that the atomic composition of Zn/O/N is 64/19/17 %. As compared with ZnO, ZnON films show much narrower band gap, lower effective electron mass, and higher carrier mobility owing to the incorporation of nitrogen. Up to 100 cm2/Vs of carrier mobility is the most noticeable advantage of ZnON.
We fabricated sub-micron ZnON TFTs with FPE scheme. One merit associated with this approach is that only one lithography process is needed. The fabricated ZnON TFTs show brilliant electrical characteristics, including excellent field-effect mobility (55~60 cm2/Vs), high ION/IOFF (108) and steep subthreshold swing (<150 mV/dec). Besides, we have also adopted alternative FPE scheme featuring discrete-gate structure of to further reduce the gate leakage current and accordingly enhance ION/IOFF. We have also demonstrated a 65 nm FPE ZnON TFT showing ION/IOFF of 108 and mobility of 8.3 cm2/Vs with e-beam lithography. These experimental results evidence the tremendous potential of ZnON films on short-channel devices.
An AlOX interfacial layer is normally seen in Al/ZnO and Al/IGZO contacts and is not observed between ZnON and Al as they are in contact. Based on the finding it is possible to improve the contact resistance of OS TFTs by adopting the ZnON as a contact layer. Such an interfacial layer can be suppressed effectively by adding a 10-nm-thick ZnON contact layer between the Al and channel layer in ZnO and IGZO TFTs. Therefore, the device characteristics are boosted significantly as the ZnON contact is inserted. Source/drain resistance (RSD) and the oxygen content in the contact interface are extracted to confirm the effectiveness of ZnON contacts. ZnON contacts are also suitable for improving the performance of logic gate circuitries, as confirmed in a 3-D OS inverter with load and driver vertically stacked. Voltage transfer curves and voltage gain of inverters are improved as the ZnON contact is introduced. Long-term stability of ZnON contacts is also investigated and the results show that ZnON is quite stable after storing for months.
Abstract (Chinese)………………………………………………………………i
Abstract (English)……………………………………………………………..iii
Acknowledgement……………………………………………………………...v
Contents………………………………………………………………………vi
Table Captions…………………………………………………………………x
Figure Captions……………………………………………………………….xii

Chapter 1 Introduction………………………………………………………...1
1.1 Overview of Metal Oxide Semiconductor…………………………………………………1
1.2 A New Oxide Semiconductor Material – Zinc Oxynitride (ZnON)……………………….3
1.3 Emerging Applications of Metal Oxide TFTs……………………………………………..6
1.4 Introduction of Film-Profile-Engineering (FPE)…………………………………………9
1.5 Objectives………………………………………………………………………………....10
1.6 Dissertation Organization………………………………………………………………...10
References…………………………………………………………………………………….23

Chapter 2 Zinc Oxynitride (ZnON) Preparation and Thin-Film Transistors (TFTs) Fabrication with Film-Profile-Engineering…………….31
2.1 Introduction……………………………………………………………………………….31
2.2 Preparation and Material Properties of ZnON……………………………………………33
2.2.1 Preparation of ZnON Thin Films………………………………………………….33
2.2.2 Material Characterization………………………………………………………….34
2.2.3 Results and Discussion…………………………………………………………….36
2.3 Fabrication and Characterization of Film-Profile Engineered ZnON TFTs with Common-Gate Structure………………………………………………………………………………....39
2.3.1 Device Fabrication………………………………………………………………...39
2.3.2 Measurement Setup and Electrical Characterization……………………………...40
2.3.2 Results and Discussion…………………………………………………………….42
2.4 Fabrication and Characterization of Film-Profile Engineered ZnON TFTs with Discrete Gate Structure………………………………………………………………………………...45
2.4.1 Device Fabrication………………………………………………………………...45
2.4.2 Results and Discussion…………………………………………………………….46
2.5 Summary………………………………………………………………………………….49
References…………………………………………………………………………………….92

Chapter 3 Fabrication and Characterization of Sub-100 nm Zinc Oxide (ZnO) and Zinc Oxynitride (ZnON) Thin-Film Transistors with Film-Profile-Engineering………………………………………97
3.1 Introduction……………………………………………………………………………...97
3.2 Device Fabrication………………………………………………………………………98
3.2.1 E-beam Lithography System and Process Conditions……………………..….…....98
3.2.2 Process Flow of ZnO and ZnON TFTs with Common Gate…………….…..….…..99
3.2.3 Process Flow of ZnO and ZnON TFTs with Discrete Gate……………………...100
3.3 Results and Discussion…………………………………………………………………..101
3.3.1 Characteristics of ZnO and ZnON TFTs with Common-Gate…………………...101
3.3.2 Characteristics of ZnO and ZnON TFTs with Discrete Gate…………………….104
3.4 Comparison with Benchmark Data from Literature for Sub-100nm OS TFTs…………106
3.5 Summary………………………………………………………………………………...107
References…………………………………………………………………………………...144
Chapter 4 Oxide-Semiconductor Thin-Film Transistors with ZnON Source/Drain Contacts……………………………………….147
4.1 Introduction……………………………………………………………………………..147
4.2 Process Flow of OS TFTs with ZnON Contact…………………………………………149
4.2.1 TFTs with Common-Gate Structure……………………………………………..149
4.2.2 TFTs with Discrete Gate Structure………………………………………………150
4.3 Results and Discussion…………………………………………………………………..150
4.3.1 ZnO TFTs with ZnON Contacts……………………………………………..…..150
4.3.2 IGZO TFTs with ZnON Contacts………………………………………………..155
4.4 Summary………………………………………………………………………………...156
References…………………………………………………………………………………...189

Chapter 5 3-Dimensional Film-Profile-Engineered Oxide Semiconductor Inverters with ZnON Contacts………………………………..194
5.1 Introduction……………………………………………………………………………..194
5.2 3-D Inverter Structure and Experimental……………………………………………….196
5.3 Results and Discussion………………………………………………………………….197
5.3.1 IGZO Inverters with ZnON Contact……………………………………………..197
5.3.2 ZnO Inverters with ZnON Contact………………………………………………200
5.3.3 Performance Comparison and Analyses of IGZO and ZnO Inverters…………...201
5.3.4 Long-Term Stability of IGZO Inverters with ZnON Contacts…………………..203
5.4 Summary………………………………………………………………………………...205
References…………………………………………………………………………………...243


Chapter 6 Conclusion and Future Work…………………………………...248
6.1 Conclusion………………………………………………………………………………248
6.2 Future Work……………………………………………………………………………..251
References…………………………………………………………………………………253

Vita……………………………………………………………………………254
Publication List………………………………………………………………255
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Chapter 4 References
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[4-15] S. W. Kim, J. C. Park, C. J. Kim, I. Song, S. Kim, S. H. Park, H. X. Yin, H. I. Lee, E. H. Lee and Y. S. Park, “Source/drain formation of self-aligned top-gate amorphous GaInZnO thin-film transistors by NH3 plasma treatment,” IEEE Elec. Dev. Lett., vol. 30, no. 4, pp. 374-376, April 2009.
[4-16] Z. Ye, L. Lu and M. Wong, “Zinc oxide thin-film transistor with self-aligned source/drain regions doped with implanted boron for enhanced thermal stability,” IEEE Trans. Elec. Dev., vol. 59, no. 2, pp. 393–399, Feb. 2012.
[4-17] R. S. Chen, W. Zhou, M. Zhang, M. Wong and H. S. Kwok, “Self-aligned indium–gallium–zinc oxide thin-film transistor with source/drain regions doped by implanted Arsenic,” IEEE Elec. Dev. Lett., vol. 34, no. 1, pp. 60-62, Jan. 2013.
[4-18] S. I. Kim, C. J. Kim, J. C. Park, I. Song, S. W. Kim, H. X. Yin, E. H. Lee, J. C. Lee and Y. S. Park, “High performance oxide thin film transistors with double active layers,” in IEDM Tech. Dig., 2008.
[4-19] J. C. Park and H. N. Lee, “Improvement of the performance and stability of oxide semiconductor thin-film transistors using double-stacked active layers,” IEEE Elec. Dev. Lett., vol. 33, no. 6, pp. 818-820, April 2012.
[4-20] M. K. Ryu, S. H. Yang, S. H. Ko Park, C. S. Hwang and J. K. Jeong, “High performance thin film transistor with cosputtered amorphous Zn–In–Sn–O channel: combinatorial approach,” Appl. Phys. Lett., vol. 95, 072104, Aug. 2009.
[4-21] J. C. Park, S. W. Kim, C. J. Kim and H. N. Lee, “The effects of gadolinium incorporation into indium–zinc oxide thin-film transistors,” IEEE Elec. Dev. Lett., vol. 33, no. 6, pp. 809-811, June 2012.
[4-22] Y. H. Tak, K. B. Kim, H. G. Park, K. H. Lee and J. R. Lee, “Criteria for ITO (indium–tin-oxide) thin film as the bottom electrode of an organic light emitting diode,” Thin Solid Films, vol. 411, no. 1, pp. 12-16, May 2002.
[4-23] Y. S. Park, H. K. Kim, S. W. Jeong and W. J. Cho, “Highly flexible indium zinc oxide electrode grown on PET substrate by cost efficient roll-to-roll sputtering process,” Thin Solid Films, vol. 518, no. 11, pp. 3071-3074, March 2010.
[4-24] Y. Ye, R. Lim and J. M. White, “High mobility amorphous zinc oxynitride semiconductor material for thin film transistors,” J. Appl. Phys., vol. 106, no. 7, p. 074512, 2009.
[4-25] M. K. Ryu, T. S. Kim, K. S. Son, H. S. Kim, J. S. Park, J. B. Seon, S. J. Seo, S. J. Kim, E. Lee, H. I. Lee, S. H. Jeon, S. W. Han and S. Y. Lee, “High mobility zinc oxynitride-TFT with operation stability under light-illuminated bias-stress conditions for large area and high resolution display applications,” in IEDM Tech. Dig., pp. 112-114, 2012.
[4-26] T. S. Kim, H. S. Kim, J. S. Park, K. S. Son, E. S. Kim, J. B. Seon, S. H. Lee, S. J. Seo, S. J. Kim, S. W. Jun, K. M. Lee, D. J. Shin, J. W. Lee, C. H. Jo, S. J. Choi, D. M. Kim, D. H. Kim, M. K. Ryu, S. H. Cho and Y. S. Park, “High performance gallium-zinc oxynitride thin film transistors for next-generation display applications,” in IEDM Tech. Dig., pp. 660-662, 2013.
[4-27] C. I. Kuan, H. C. Lin, P. W. Li, and T. Y. Huang, “High-performance submicrometer ZnON thin-film transistors with record field-effect mobility,” IEEE Elec, Dev. Lett., vol. 37, no. 3, pp. 303-305, Mar. 2016.
[4-28] R. J. Lyu, H. C. Lin, M. H. Wu, B. S. Shie, H. T. Hung, and T. Y. Huang, “Film profile engineering (FPE): A new concept for manufacturing of short-channel metal oxide TFTs,” in IEDM Tech. Dig., 2013, pp. 288–291.
[4-29] H. C. Lin, R. J. Lyu, and T. Y. Huang, “Fabrication of high-performance ZnO thin-film transistors with submicrometer channel length,” IEEE Elec. Dev. Lett., vol. 34, no. 9, pp. 1160–1162, Sep. 2013.
[4-30] R. J. Lyu, H. C. Lin and T. Y. Huang, “Implementation of film profile engineering in the fabrication of ZnO thin-film transistors,” IEEE Trans. Elec. Dev., vol. 61, no. 5, pp. 1417–1422, May 2014.
[4-31] J. P. Campbell, K. P. Cheung, J. S. Suehle, and A. Oates, “A simple series resistance extraction methodology for advanced CMOS devices,” IEEE Elec. Dev. Lett., vol. 32, no. 8, pp. 1047–1049, Aug. 2011.

Chapter 5 References
[5-1] K. Kaneko, N. Inoue, S. Saito, N. Furutake, and Y. Hayashi, “A novel BEOL transistor (BETr) with InGaZnO embedded in Cu-interconnects for on-chip high voltage I/Os in standard CMOS LSIs,” in Symp. VLSI. Technol., pp. 120–123, June, 2011.
[5-2] H. Sunamura, K. Kaneko, N. Furutake, S. Saito, M. Narihiro, M. Hane and Y. Hayashi, “High-voltage complementary BEOL-FETs on Cu interconnects using n-type IGZO and p-type SnO dual oxide semiconductor channels,” in Symp. VLSI Technol., pp. 250–251, June, 2013.
[5-3] K. Kaneko, H. Sunamura, M. Narihiro, S. Saito, N. Furutake, M. Hane, and Y. Hayas, “Operation of functional circuit elements using BEOL-transistor with InGaZnO channel for on-chip high/low voltage bridging I/Os and high-current switches,” in Symp. VLSI Technol., pp. 123–124, June, 2012.
[5-4] S. H. Wu, X. Y. Jia, M. Kai, C. C. Shuai, T. Y. Hsieh, H. C. Lin, D. Chen, C. B. Lin, J. Y. Wu, T. R. Yew, Y. Endo, K. Kato, and S. Yamazaki, “Extremely low power c-axis aligned crystalline In-Ga-Zn-O 60 nm transistor integrated with industry 65 nm Si MOSFET for IoT normally-off CPU application,” in Symp. VLSI Technol., June, 2016.
[5-5] S. H. Wu, X. Y. Jia, X. Li, C. C. Shuai, H. C. Lin, M. C. Lu, T. H. Wu, M. Y. Liu, J. Y. Wu, D. Matsubayashi, K. Kato, and S. Yamazaki, “Performance boost of crystalline In-Ga-Zn-O material and transistor with extremely low leakage for IoT normally-off CPU application,” in Symp. VLSI Technol., pp. 166-167, June, 2017.
[5-6] I C. Chiu, Y. S. Li, M. S. Tu and I C. Cheng, “Complementary oxide–semiconductor-based circuits with n-channel ZnO and p-channel SnO thin-film transistor,” IEEE Elec. Dev. Lett., vol. 35, no. 12, pp. 1263–1265, Nov. 2014.
[5-7] Dhananjay, C. W. Chu, C. W. Ou, M. C. Wu, Z. Y. Ho, K. C. Ho and S. W. Lee, “Complementary inverter circuits based on p-SnO2 and n-In2O3 thin film transistors,” Appl. Phys. Lett., vol. 92, no. 23, 232103, June 2008.
[5-8] P. T. Liu, Y. T. Chou, L. F. Teng and C. S. Fuh, “High-gain complementary inverter with InGaZnO/pentacene hybrid ambipolar thin film transistors,” Appl. Phys. Lett., vol. 97, no. 8, 083505, Aug. 2010.
[5-9] M. J. Seok, M. H. Choi, M. Mativenga, D. Geng, D. Y. Kim and J. Jang, “A full-swing a-IGZO TFT-based inverter with a top-gate-bias-induced depletion load,” IEEE Elec. Dev. Lett., vol. 32, no. 8, pp. 1089–1091, Aug. 2011.
[5-10] H. Luo, P. Wellenius, L. Lunardi and J. F. Muth, “Transparent IGZO-based logic gates,” IEEE Elec. Dev. Lett., vol. 33, no. 5, pp. 673–675, May 2012.
[5-11] M. Mativenga, M. H. Choi, J. W. Choi and J. Jang, “Transparent flexible circuits based on amorphous-indium–gallium–zinc–oxide thin-film transistors,” IEEE Elec. Dev. Lett., vol. 32, no. 2, pp. 170–172, Dec. 2010.
[5-12] K. C. Sanal, L. S. Vikas, M. K. Jayaraj, “Room temperature deposited transparent p-channel CuO thin film transistors,” Appl. Surf. Sci., vol. 297, pp. 153–157, 2014.
[5-13] X. Huang, C. Wu, H. Lu, F. Ren, D. Chen, Y. Liu, G. Yu, R. Zhang, Y. Zheng and Y. Wang, “Large-swing a-IGZO inverter with a depletion load induced by laser annealing,” IEEE Elec. Dev. Lett., vol. 35, no. 10, pp. 1034–1036, Oct. 2014.
[5-14] J. M. Lee, I. T. Cho, J. H. Lee and H. I. Kwon, “Full-swing InGaZnO thin film transistor inverter with depletion load,” Jpn. J. Appl. Phys., vol. 48, no. 10R, Oct. 2009.
[5-15] L. J. Chi, M. J. Yu, Y. H. Chang, T. H. Hou, “1-V Full-Swing Depletion-Load a-In–Ga–Zn–O Inverters for Back-End-of-Line Compatible 3D Integration,” IEEE Elec. Dev. Lett., vol. 37, no. 4, pp. 441– 444, April 2016.
[5-16] G. J. Lee, J. Kim, J. H. Kim, S. M. Jeong, J. E. Jang and J. Jeong, “High performance, transparent a-IGZO TFTs on a flexible thin glass substrate,” Semicond. Sci. Technol., vol. 29, no. 3, 035003, Jan. 2014.
[5-17] T. H. Hwang, I. S. Yang, O. K. Kwon, M. K. Ryu, C. W. Byun, C. S. Hwang and S. H. K. Park, “Inverters using only n-type indium gallium zinc oxide thin film transistors for flat panel display applications,” Jpn. J. Appl. Phys., vol. 50, no. 3S, March 2011.
[5-18] J. Kim, S. M. Jeong and J. Jeong, “Scaling characteristics of depletion type, fully transparent amorphous indium–gallium–zinc-oxide thin-film transistors and inverters following Ar plasma treatment,” Jpn. J. Appl. Phys., vol. 54, no. 11, Oct. 2015.
[5-19] H. S. Lee, C. H. Park, K. H. Lee, D. H. Kim, H. R. Kim, G. H. Lee, S. Im, “Threshold voltage control by gate electrode in Ga–Sn–Zn–O thin‐film transistors for logic inverter application,” Phys. Status Solidi RRL, vol. 5, no. 5-6, pp. 211-213, May 2011.
[5-20] J. Leppäniemi, K. Eiroma, H. S. Majumdar and A. Alastalo, “In2O3 thin-film transistors via inkjet printing for depletion-load NMOS inverters,” IEEE Elec. Dev. Lett., vol. 37, no. 4, pp. 445– 448, April 2016.
[5-21] R. J. Lyu, H. C. Lin, M. H. Wu, B. S. Shie, H. T. Hung and T. Y. Huang, “Film profile engineering (FPE): A new concept for manufacturing of short-channel metal oxide TFTs,” in IEDM Tech. Dig., pp.288-291, 2013.
[5-22] R. J. Lyu, H. C. Lin and T. Y. Huang, “Fabrication and characterization of film profile engineered ZnO TFTs with discrete gates,” IEEE J. Elec. Dev. Soc., vol. 3, no. 3, pp. 260–266, Mar. 2015.
[5-23] H. C. Lin, M. H. Wu, C. W. Chan, R. J. Lyu, and T. Y. Huang, “Novel InGaZnO inverters utilizing film profile engineering,” Jpn. J. Appl. Phys., vol. 54, no. 081102, July 2015.
[5-24] R. J. Lyu, H. C. Lin, P. W. Li and T. Y. Huang, “A film-profile-engineered 3-D InGaZnO inverter technology with systematically tunable threshold voltage,” IEEE Trans. Elec. Dev., vol. 63, no. 9, pp. 3533–3539, Sep. 2016.
[5-25] C. I. Kuan, H. C. Lin and P. W. Li, “Improving the performance of ZnO thin-film transistors with ZnON source/drain contacts,” IEEE Trans. Elec. Dev., vol. 64, no. 7, pp. 2849–2853, July. 2017.
[5-26] A. S. Sedra and K. C. Smith, “The MOSFET as an amplifier and as a switch,” in Microelectronic Circuits 5th ed. New York, NY, USA: Oxford University Press, 2004, pp. 270~279.
[5-27] J. P. Campbell, K. P. Cheung, J. S. Suehle, and A. Oates, “A simple series resistance extraction methodology for advanced CMOS devices,” IEEE Elec. Dev. Lett., vol. 32, no. 8, pp. 1047~1049, Aug. 2011.
[5-28] S. Y. Sung, J. H. Choi, U. B. Han, K. C. Lee, J. H. Lee, J. J. Kim, W. Lim, S. J. Pearton, D. P. Norton and Y. W. Heo, “Effects of ambient atmosphere on the transfer characteristics and gate-bias stress stability of amorphous indium-gallium-zinc oxide thin-film transistors,” Appl. Phys. Lett., vol. 96, no. 102107, March 2010.
[5-29] N. Tiwari, R. N. Chauhan, H. P. D. Shieh, P. T. Liu and Y. P. Huang, “Photoluminescence and reliability study of ZnO cosputtered IGZO thin-film transistors under various ambient conditions,” IEEE Trans. Elec. Dev., vol. 63, no. 4, pp. 1578~1581, Feb. 2016.
[5-30] K. Yamada, K. Nomura, K. Abe, S. Takeda, and H. Hosono, “Examination of the ambient effects on the stability of amorphous indium-gallium-zinc oxide thin film transistors using a laser-glass-sealing technology,” Appl. Phys. Lett., vol. 105, no. 133503, Sep. 2014.
[5-31] Y. C. Chen, T. C. Chang, H. W. Li, S. C. Chen, W. F. Chung, Y. H. Chen, Y. H. Tai, T. Y. Tseng and F. S. Yeh(Huang), “Surface states related the bias stability of amorphous In–Ga–Zn–O thin film transistors under different ambient gasses,” Thin Solid Films, vol. 520, no. 5, Dec. 2011.
[5-32] S. Y. Huang, T. C. Chang, M. C. Chen, S. C. Chen, C. T. Tsai, M. C. Hung, C. H. Tu, C. H. Chen, J. J. Chang and W. L. Liau, “Effects of ambient atmosphere on electrical characteristics of Al2O3 passivated InGaZnO thin film transistors during positive-bias-temperature-stress operation,” Electrochem. Solid-State Lett., vol. 14, no. 4, pp. H177~H179, Feb. 2011.
[5-33] J. K. Jeon, J. G. Um, S. Lee, and J. Janga, “Control of O-H bonds at a-IGZO/SiO2 interface by long time thermal annealing for highly stable oxide TFT,” AIP Advances, vol. 7, no. 125110, Dec. 2017.
[5-34] S. I Oh, J. M. Woo, and J. H. Jang, “Comparative Studies of Long-Term Ambiance and Electrical Stress Stability of IGZO Thin-Film Transistors Annealed Under Hydrogen and Nitrogen Ambiance,” IEEE Trans. Elec. Dev., vol. 63, no. 5, pp. 1910~1915, May 2016.
[5-35] S. J. Jokela and M. D. McCluskey, “Structure and stability of O−H donors in ZnO from high-pressure and infrared spectroscopy,” Phys. Rev. B, vol. 72, no. 113201, Sep. 2005.
[5-36] G. A. Shi, M. Stavola, S. J. Pearton, M. Thieme, E. V. Lavrov, and J. Weber, “Hydrogen local modes and shallow donors in ZnO,” Phys. Rev. B, vol. 72, no. 195211, Nov. 2005.

Chapter 6 References
[6-1] R. J. Lyu, H. C. Lin, P. W. Li and T. Y. Huang, “A film-profile-engineered 3-D InGaZnO inverter technology with systematically tunable threshold voltage,” IEEE Trans. Elec. Dev., vol. 63, no. 9, pp. 3533–3539, Sep. 2016.
[6-2] E. Lee, T. Kim, A. Benayad, H. Kim, S. Jeon, and G. S. Park, “Ar plasma treated ZnON transistor for future thin film electronics,” Appl. Phys. Lett., vol. 107, 122105, Sep. 2015.
[6-3] J. T. Jang, J. Park, B. D. Ahn, D. M. Kim, S. J. Choi, H. S. Kim, and D. H. Kim, “Study on the photoresponse of amorphous In−Ga−Zn−O and zinc oxynitride semiconductor devices by the extraction of sub-gap-state distribution and device simulation,” ACS Appl. Mater. Interfaces, vol. 7, no. 28, pp. 15570-15577, June 2015.
[6-4] S. Salahuddin, “Review of negative capacitance transistors,” in VLSI-TSA, April 2016.
[6-5] S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” ACS Nano Lett., vol. 8, no. 2, Dec. 2007.
[6-6] K. S. Li, P. G. Chen, T. Y. Lai, C. H. Lin, C. C. Cheng, C. C. Chen, Y. J. Wei, Y. F. Hou, M. H. Liao, M. H. Lee, M. C. Chen, J. M. Sheih, W. K. Yeh, F. L. Yang, S. Salahuddin, C. Hu, “Sub-60mV-swing negative-capacitance FinFET without hysteresis,” in IEDM Tech Dig., pp.620-623, 2015.
[6-7] H. Sunamura, K. Kaneko, N. Furutake, S. Saito, M. Narihiro, M. Hane, and Y. Hayashi, "High-voltage complementary BEOL-FETs on Cu interconnects using n-type IGZO and p-type SnO dual oxide semiconductor channels," in Symp. VLSI Technol., pp. 250-251, June 2013.
[6-8] S. H. Wu, X. Y. Jia, M. Kui, C. C. Shuai, T. Y. Hsieh, H. C. Lin, D. Chen, C. B. Lin, J. Y. Wu, T. R. Yew, Y. Endo, K. Kato and S. Yamazaki, "Extremely low power c-axis aligned crystalline In-Ga-Zn-O 60 nm transistor integrated with industry 65 nm Si MOSFET for IoT normally-off CPU application," in Symp. VLSI Technol., June 2016.
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