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研究生:廖子響
研究生(外文):Liao, Tzu-Hsiang
論文名稱:一個十七位元應用於音頻之三角積分調變器
論文名稱(外文):A 1-V 17-Bit Delta-Sigma Modulator ADC for Audio Applications
指導教授:吳介琮
指導教授(外文):Wu, Jieh-Tsorng
口試委員:郭建男洪浩喬
口試委員(外文):Kuo, Chien-NanHong, Hao-Chiao
口試日期:2019-06-14
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:76
中文關鍵詞:三角積分調變器類比數位轉換器開關電容式積分器分段式積分積分器
外文關鍵詞:Delta-Sigma ModulatorAnalog-to-Digital ConveterSwitched-Capacitor IntegratorSegmented-Integration Integrator
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本論文主要實現一個使用台積電二十八奈米製程,輸入訊號頻寬為兩萬五千赫茲,供應電壓一伏特,每秒六百四十萬赫茲採樣的三角積分調變器,主要作為音頻類比數位轉換器之應用。在三階級串列積分器分佈式前饋架構下,於其前端加入一個低精準度的連續漸進式類比數位轉換器,使輸入訊號先被其作粗略的量化,再將電壓殘餘值饋入三角積分調變器進行處理。因此大幅降低迴路濾波器內部積分器的積分電容,間接降低積分器的功率消耗。同時因為三角積分器調變器需要的輸入範圍較小,系統的動態範圍也能有所提升。在積分器的設計上,我們採用了分段式積分的積分器技術,優化第一級放大器的功率消耗。由於系統解析度高,我們加入資料加權平均演算法處理電容的布匹配效應,以及利用截波電路將閃爍雜訊搬移除訊號的頻寬。
本電路經由Matlab和Verilog-AMS做系統驗證,再以台積電二十八奈米的互補式金氧半導體製程參數來設計與模擬。在消耗功率一百八十五微瓦之下達到訊號雜訊比103.29 dB。該三角積分調變器的效能指標為184.5 dB。
This thesis presents a micro-power audio delta-sigma modulator. This work is simulated in TSMC 28-nm CMOS process, and it operates under 25kHz bandwidth and 6.4MHz sampling frequency. The supply voltage is 1V. By a coarse SAR (successive approximation register) ADC in front of the fine delta-sigma modulator, the input signal is transferred into 6-bit residue voltage which will be fed into delta-sigma modulator. The coarse SAR ADC makes the capacitor of integrator much smaller, also the power consumption of the first integrator. Moreover, the dynamic range of delta-sigma modulator increased because the signal that delta-sigma processed is low. We adopt Segmented Integration method to optimize the power consumption of the first integrator. Since linearity is a critical specification in our circuit, we use data weighted averaging technique to enhance the linearity of DAC, and we employ chopper circuits to cope with flicker noise.
We firstly simulate the behavior model with Matlab and Verilog-AMS. Then, the circuit is designed and simulated in TSMC 28-nm CMOS process. It achieves 103.29 dB SNDR, in a 25 kHz bandwidth, while dissipating only 185.6 μW. The figure-of-merit of the DSM is 184.5 dB.
中文摘要 i
English Abstract ii
誌謝 iii
表目錄 vii
圖目錄 viii
1 結論 1
1.1 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 論文組織. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 三角積分調變器工作原理 4
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 類比數位轉換器基礎原理. . . . . . . . . . . . . . . . . . . 4
2.3 奈奎斯特取樣定理. . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 量化與量化雜訊. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 超取樣. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 三角積分調變器之雜訊整形. . . . . . . . . . . . . . . . . 7
2.7 高階級雜訊整形. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 三角積分調變器效能衡量標準. . . . . . . . . . . . . . 12
2.8.1 訊號雜訊比. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.8.2 訊號雜訊失真比. . . . . . . . . . . . . . . . . . . . . . . . 12
2.8.3 動態範圍. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8.4 有效位元數. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 SAR DSM 類比數位轉換器 13
3.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 兩步式轉換. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 殘餘電壓值前饋電路實現. . . . . . . . . . . . . . . . . . . 14
3.4 兩部式轉換輸入範圍調整. . . . . . . . . . . . . . . . . . . 15
3.5 系統轉移函數分析. . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 兩步式轉換系統規格設計. . . . . . . . . . . . . . . . . . . 19
3.7 結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 一個每秒六四十萬次採樣頻率之三角積分調變器設計 22
4.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 規格目標. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 架構決定. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 系統行為階層模擬. . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1 運算放大器有限增益. . . . . . . . . . . . . . . . . . . . . 27
4.4.2 運算放大器單增益頻寬與迴轉率. . . . . . . . . . . 29
4.4.3 熱雜訊效應. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5 分段式積分技術原理. . . . . . . . . . . . . . . . . . . . . . . 34
4.6 資料權重平均電路. . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7 截波穩定技術. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7.1 運算放大器輸入級MOS電晶體最佳化. . . . . . .38
4.7.2 相關雙取樣技術. . . . . . . . . . . . . . . . . . . . . . . . . 39
4.7.3 截波穩定技術. . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.8 結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5 電路設計與模擬結果 41
5.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 兩步式轉換之三角積分調變器. . . . . . . . . . . . . . . 41
5.3 運算放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4 調變器與解調變器. . . . . . . . . . . . . . . . . . . . . . . . . 52
5.5 量化器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.6 靴帶式開關電路. . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.7 資料權重平均電路. . . . . . . . . . . . . . . . . . . . . . . . . 58
5.8 連續漸進式類比數位轉換器. . . . . . . . . . . . . . . . . 60
5.9 系統時序. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.10 模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 67
6 結論與建議 69
6.1 結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2 建議研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
參考文獻 71
自傳 76
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