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研究生:朱晏承
研究生(外文):Zhu, Yan-Cheng
論文名稱:良率驅使增置電源凸塊以強化電源供應網絡可靠度
論文名稱(外文):Global Yield-Driven Redundant Power Bump Assignment for Power Network Robustness
指導教授:李育民李育民引用關係
指導教授(外文):Lee, Yu-Min
口試委員:吳霖堃陳宏明陳富強
口試委員(外文):Wu, Lin-KunChen, Hung-MingChen, Fu-Chiang
口試日期:2018-09-28
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:107
語文別:英文
論文頁數:66
中文關鍵詞:自動化設計電源供應網絡增置電源凸塊封裝電源凸塊良率良率估計
外文關鍵詞:EDApower networkredundant power bumpmanufacturing package processpower bump yieldyield estimation
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在晶片的封裝過程中,電源凸塊會有不完整連接的狀況這會使裝置沒辦法正常的操作進而降低電源供應網絡的良率。本篇論文要闡述的是考慮電源凸塊的良率去增置電源凸塊。藉由準確的量化出裝置與可靠度之間的關係以及電源供應網絡與可靠度之間的關係,利用上述兩點,精準地增置電源凸塊並且使電源凸塊使用量最少。
During the package manufacturing process, open defect of power bumps may cause insufficient power supply and degrade the power network yield. This work presents a redundant power bump insertion method to ensure power integrity by considering the power bump yields. The proposed method can efficiently assign redundant bumps by accurately estimating the load and power network yield and minimize the amounts of redundant power bumps to enhance the power network yield.
1 Introduction . . . . . . . . . . . . . . . . . . .1
1.1 Motivation . . . . . . . . . . . . . . . . . . .1
1.2 Related Work . . . . . . . . . . . . . . . . . . 2
1.2.1 Power Network . . . . . . . . . . . . . . . . .2
1.2.2 Flip Chip Package . . . . . . . . . . . . . . .3
1.2.3 Single-Bump Failure Method [1] . . . . . . . . 3
1.3 Our Contribution . . . . . . . . . . . . . . . . 4
1.4 Organization of the Thesis . . . . . . . . . . . 4
2 Preliminaries . . . . . . . . . . . . . . . . . . .6
2.1 Power Bump Yield Model [2] . . . . . . . . . . . 6
2.2 Equivalent Circuit and Modified Nodal Analysis . 8
2.3 Definition of Load Yield and Chip Yield . . . . .9
2.4 Single-Bump Failure Method [1] . . . . . . . . . 9
2.5 Load Yield Estimation by Two Zone Method [3] . . 11
2.6 Problem Formulation . . . . . . . . . . . . . . .12
3 Load Yield and Chip Yield Estimation . . . . . . . 14
3.1 Find One Voltage Contribution of Each Power Bump 14
3.2 Math Form . . . . . . . . . . . . . . . . . . . .16
3.3 Load Yield Estimation by Two Set Method . . . . .18
3.4 Chip Yield Estimation by Two Set Method . . . . .24
3.5 Update Vc Locality . . . . . . . . . . . . . . . 28
4 Redundant Power Bump Assignment Algorithm . . . . .30
4.1 Design Flow . . . . . . . . . . . . . . . . . . .30
4.2 Worst Load Yield Region . . . . . . . . . . . . .31
5 Verification by Monte-Carlo Method . . . . . . . . 33
5.1 Verification Flow . . . . . . . . . . . . . . . .33
5.2 Termination Criteria [4] . . . . . . . . . . . . 34
6 Experimental Results . . . . . . . . . . . . . . . 35
6.1 Redundant Power Bumps Improvement . . . . . . . .36
6.2 Accuracy of Load Yield Estimation . . . . . . . .41
6.3 Accuracy of Chip Yield Estimation . . . . . . . .42
7 Conclusion and Future Work . . . . . . . . . . . . 45
Appendix A Load Yield Accuracy Illustration . . . . .47
Appendix B Load Yield Accuracy Statistic . . . . . . 54
Appendix C Accuracy of Load Yield with nf ail;max . .56
Appendix D Accuracy of Chip Yield with Vc Updating . 58
Appendix E Chip Yield Improvement with Exhaustive Method 60
E.1 Assign Redundant Power Bumps Based by SA Method .60
E.2 Assign Redundant Power Bumps Based by Greedy Method . 61
E.3 Comparison with Assignment Method . . . . . . . 61
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