臺灣博碩士論文加值系統

本論文深入地討論中高解析度的低速循序漸進式類比數位轉換器之設計考量，文中所提及之三個類比數位轉換器皆為應用於生醫電子之醫療晶片，例如骨導式人工電子耳之體外訊號接收器。電路設計與製造採用台灣積體電路製造股份有限公司（ TSMC ）1P6M 0.18µm互補式金屬氧化物半導體（ CMOS ）製程。
晶片(一)為操作於47KS/s的10位元SAR ADC，採單調式切換架構，因數位電路走線精簡而達2.6μW的極低功耗。在正常操作頻率下，輸入全幅1.8VPP，量測得9.77位元的有效位數、60.55dB的SNDR和82.18dB的SFDR，而佈局面積為598μm×786μm，FOM為63 fJ/Conv.step。晶片(二)為操作於62KS/s的12位元免校正SAR ADC，採共模式切換架構並納入冗位電容吸收比較器與參考電壓誤差。在正常操作頻率下，輸入全幅1.8VPP，量測8顆晶片得平均有效位數為11位元、SNDR為68dB、SFDR為83dB、輸入參考雜訊為209μV、平均功耗為6.7μW，得到53 fJ/Conv.step的FOM，而佈局面積為587μm×599μm。晶片(三)同為操作於62KS/s的12位元SAR ADC，但帶有類比校正電路，能夠偵測特定的暫存數位碼，根據比較器輸出結果對電容誤差予以量化並校正。在不開啟校正功能的情況下，輸入全幅1.8VPP，量測8顆晶片得平均有效位數10.4位元、SNDR為64.4dB、SFDR為73dB、輸入參考雜訊為193μV、平均功耗為7.4μW；而開啟校正功能的情況下，同樣條件量測8顆晶片得平均有效位數10.8位元、SNDR為66.6dB、SFDR為79dB、輸入參考雜訊為235μV、平均功耗為9μW，得83 fJ/Conv.step的FOM，而佈局面積為560μm×350μm。

In this thesis, the design consideration of low-speed, mid/high resolution successive approximation register analog-to-digital converters (SAR ADCs) is discussed in depth. The three mentioned ADCs are all designed for biomedical applications, such as the external signal receiver of bone-guided cochlear implants. All the ICs were fabricated by using 0.18-μm 1P6M TSMC CMOS process.
The first IC is a 10-bit 47KS/s SAR ADC which adopts monotonic switching technique. Due to the layout simplicity of the digital blocks, the power consumption is as low as 2.6μW. At normal sampling rate and provided with a 1.8VPP input signal, the measured ENOB, SNDR and SFDR are 9.77-bit, 60.55dB, and 82.18dB, respectively. It occupies an area of 598μm×786μm and the FOM is 63 fJ/conv.step. The second one is a 12-bit 62KS/s calibration-free SAR ADC which adopts VCM-based switching technique and includes redundant capacitors to counter comparator offset and reference voltage error. At normal sampling rate and provided with a 1.8VPP input signal, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 11-bit, 68dB, 83dB, 209μV, and 6.7μW, respectively. It occupies an area of 587μm×599μm and the FOM is 53 fJ/conv.step. The third one is also a 12-bit 62KS/s SAR ADC, but with analog background calibration circuit, which quantizes and calibrates the capacitor mismatch error according to the comparator output while certain codes in the register are detected. While disabling the calibration feature and provided with a 1.8VPP input signal, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 10.4-bit, 64.4dB, 73dB, 193μV, and 7.4μW, respectively. While enabling the calibration feature and under the same circumstance, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 10.8-bit, 66.6dB, 79dB, 235μV, and 9μW, respectively. It occupies an area of 560μm×350μm and the FOM is 83 fJ/conv.step.

摘要 ii
ABSTRACT iv
誌謝 vi
圖目錄 x
表目錄 xv
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章 類比數位轉換器概論 3
2.1 類比數位轉換器的基本介紹 3
2.2 類比數位轉換器的規格參數 4
2.2.1 取樣 4
2.2.2 量化 5
2.2.3 偏移誤差與增益誤差 7
2.2.4 微分非線性誤差 7
2.2.5 積分非線性誤差 9
2.2.6 訊號雜訊比 9
2.2.7 訊號雜訊失真比 11
2.2.8 無雜散動態範圍 11
2.2.9 動態範圍 12
2.2.10 效能參數 12
2.3 類比數位轉換器架構 13
2.3.1 快閃式類比數位轉換器 13
2.3.2 管線式類比數位轉換器 14
2.3.3 循續漸近式類比數位轉換器 15
2.3.4 三角積分調變類比數位轉換器 15
2.3.5 總結 16
第三章 電路設計與實現 18
3.1 十位元48KS/s低功耗SAR ADC設計 18
3.1.1 靴帶式開關 19
3.1.2 動態比較器 21
3.1.3 SAR Logic數位電路 29
3.1.4 DAC開關電路 31
3.1.5 電容陣列佈局考量 32
3.2 十二位元62KS/s低功耗SAR ADC設計 33
3.2.1 冗位電容 33
3.2.2 雙級動態比較器 38
3.2.3 SAR Logic數位電路 41
3.2.4 DAC開關電路 43
3.2.5 電容陣列設計 43
3.3 帶類比背景校正電路之十二位元62KS/s SAR ADC設計 48
3.3.1 背景校正電路 51
第四章 電路模擬與量測結果 58
4.1 10位元48KS/s循序漸進式類比數位轉換器 58
4.1.1 佈局前模擬 58
4.1.2 佈局電路圖與佈局後模擬 59
4.1.3 晶片實現與量測結果 61
4.2 12位元62KS/s免校正循序漸進式類比數位轉換器 64
4.2.1 佈局前模擬 64
4.2.2 佈局電路圖與佈局後模擬 65
4.2.3 考慮非理想因素之行為模擬 66
4.2.4 晶片實現與量測結果 67
4.3 12位元62KS/s帶校正電路之循序漸進式類比數位轉換器 72
4.3.1 佈局前模擬 72
4.3.2 佈局電路圖與佈局後模擬 73
4.3.3 考慮非理想因素之行為模擬 75
4.3.4 晶片實現與量測結果 76
第五章 結論與未來展望 82
5.1 結論 82
5.2 未來展望 83
參考文獻 84

[1] Chun-Cheng Liu , Guan-Ying Huang, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4,pp731-740,April 2010
[2] Brian P. Ginsburg and Anantha P. Chandrakasan, “ 500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC “IEEE J. Solid-State Circuits, vol. 42, no. 4,pp739-747,April 2007
[3] Yan Zhu,, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin,, Seng-Pan U, Rui Paulo Martins,Franco Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS ” IEEE J. Solid-State Circuits, vol. 45, no. 6,pp1111-1121,June 2010.
[4] Yue Wu , Xu Cheng and Xiaoyang Zeng, “A Split-capacitor Vcm-based Capacitor-switching Scheme for Low-power SAR ADCs ”IEEE ISCAS,pp2014-2017,2013.
[5] Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, and Franco Maloberti, “Split-SAR ADCs: Improved Linearity With Power and Speed Optimization,” IEEE Trans. Biomed. Circuits Syst., vol. 22, no. 2, pp. 372–383, Feb. 2014..
[6] B. Razavi, 1999 ISSCC Short Course
[7] Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, and Geert Van der Plas, “Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441–1454, JULY. 2008.
[8] Min-Kyu Kim, Seong-Kwan Hong, and Oh-Kyong Kwon, M, “An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors,” IEEE Trans. Electron Devices, vol. 63, no. 9, sep. 2016.
[9] Asad A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, Aug. 2006.
[10] T. Sepke, P. Holloway, C. G. Sodini, H.-S. Lee, "Noise analysis for comparator-based circuits", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 58, no. 3, pp. 541-553, Mar. 2009.
[11] J. Cheon, G. Han, "Noise analysis and simulation method for a single-slope ADC with CDS in a CMOS image sensor", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 55, no. 10, pp. 2980-2987, Nov. 2008.
[12] D. Levski,M. Want,B.Choubey “Ramp Noise Projection in CMOS Image Sensor Single-Slope ADCs” , IEEE Trans. Circuits Syst. I Reg. Papers, vol. 64, no. 6, pp. 1380-1389, Jun. 2017.
[13] K. Ki-Duk, B. San-Ho, C. Yoon-Kyung, B. Jong-Hak, C. Hwa-Hyun, P. Jong-Kang, et al., "A capacitive touch controller robust to display noise for ultrathin touch screen displays," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pp. 116-117, 2012.
[14] R. Schreier, J. Silva, J. Steensgaard “ Design-oriented estimation of thermal noise in switched-capacitor circuits” IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 2358-2367, Nov. 2005.
[15] John K. Fiorenza, Todd Sepke, Peter Holloway ”Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658-2668, Dec. 2006..
[16] Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, Nai-Kuan Chou, and Chorng-Kuang Wang, “A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications,” IEEE Asian Solid-State Circuits Conference, pp. 149–152, Nov. 2009.
[17] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13μm CMOS for medical implant devices,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1585–1593, Jul. 2012.
[18] Saisundar. S , Jia Hao Cheong and Minkyu Je, “A 1.8V 1MS/s Rail-to-Rail 10-bit SAR ADC in 0.18μm CMOS,” IEEE Radio-Frequency Integration Technology (RFIT), pp. 83–85, Nov. 2014
[19] S. Fateh, P. Schonle, L. Bettini, G. Rovere, L. Benini, and Q. Huang, “A reconfigurable 5-to-14 bit SAR ADC for battery-powered medical instrumentation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 11, pp. 2685–2694, Nov. 2015.
[20] Min-Kyu Kim, Seong-Kwan Hong, and Oh-Kyong Kwon, M, “An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors,” IEEE Trans. Electron Devices, vol. 63, no. 9, sep. 2016.
[21] Y. C. Chae et al., “A 2.1 M pixels, 120 frame/s CMOS image sensor with column-parallel ADC architecture,” IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 236–247, Jan. 2011.
[22] S. Matsuo et al., “8.9-megapixel video image sensor with 14-b columnparallel SA-ADC,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2380–2389, Nov. 2009..
[23] F. Tang, D. G. Chen, B. Wang, and A. Bermak, “Low-power CMOS image sensor based on column-parallel single-slope/SAR quantization scheme,” IEEE Trans. Electron Devices, vol. 60, no. 8, pp. 2561–2566, Aug. 2013.
[24] F. Tang, B. Wang, A. Bermak, X. Zhou, S. Hu, and X. He, “A columnparallel inverter-based cyclic ADC for CMOS image sensor with capacitance and clock scaling,” IEEE Trans. Electron Devices, vol. 63, no. 1, pp. 162–167, Jan. 2016.
[25]N. Verma and A. Chandrakasan, “A 25µW 100 kS/s 12 bit ADC for wireless micro-sensor applications,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 222–223.
[26]N. Verma and A. P. Chandrakasan, "An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes," Solid-State Circuits, IEEE Journal of, vol. 42, pp. 1196-1205, 2007.
[27]H. Tong-Hun, C. Wen-Hai, Y. Ik-Seok, and K. Oh-Kyong, "A highly area-efficient controller for capacitive touch screen panel systems," Consumer Electronics, IEEE Transactions on, vol. 56, pp. 1115-1122, 2010.
[28]K. Hyoung-Rae, C. Yoon-Kyung, B. San-Ho, K. Sang-Woo, C. Kwang-Ho, A. Hae-Yong, et al., "A mobile-display-driver IC embedding a capacitive-touch-screen controller system," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, pp. 114-115, 2010.
[29]X.-H. Qian et al., “A bone-guided cochlear implant CMOS microsystem preserving acoustic hearing,” in Proc. Int. Symposium on VLSI Circuits. IEEE, 2017, pp. C46–C47.
[30]F.-G. Zeng, S. Rebscher, W. Harrison, X. Sun, and H. Feng, “Cochlear implants: system design, integration, and evaluation,” IEEE Rev.Biomed. Eng., vol. 1, pp. 115–142, Dec. 2008.
[31]P. J. A. Harpe, C. Zhou, Y. Bi, N. P. van derMeijs, X. Wang, K. Philips, G. Dolmans, and H. de Groot, “A 26 8 bit 10 MS/s asynchronous SAR ADC for low energy radios,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1585–1595,Jul. 2011
[32]F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176–177.
[33]J. L. McCreary, P. R. Gray, "All-MOS charge redistribution analog-to-digital conversion techniues—Part I",IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 371-379, Dec. 1975.
[34]C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92 mW 10-bit50-MS/s SAR ADC in 0.13 m CMOS process,” in IEEE Symp. VLSICircuits Dig., Jun. 2009, pp. 236–237.