實驗室以務實軟體定義無線電(Software-defined Radio,SDR)來實現DVB-T接收機，結合FPGA(XC7A200T)及射頻模組(AD9361)完成軟體定義無線電平台，本論文設計基頻電路來進行DVB-T訊號解調，基頻接收機需要的模組包括降頻取樣、時間同步、頻率同步、快速傅立葉轉換、通道估測等化、符元解交錯器、軟式決策、位元解交錯器、迴旋碼解碼、外部解交錯器、里德所羅門碼解碼、解亂碼器，將解調解碼得到之MPEG-2傳輸封包資料流用VLC多媒體播放器播出。
先實錄訊號以Matlab進行解調，再使用硬體描述語言設計基頻電路，用iSim模擬電路時序後，再以軟體定義無線電平台實錄訊號驗證其硬體功能，經過解調解碼後，便能夠得到MPEG-2(Moving Picture Experts Group, MPEG) Transport Stream，將之播放以驗證接收機之成果。

Our laboratory use Realistic Software-defined Radio platform to implement Digital Video Broadcasting Terrestrial(DVB-T) receiver. We combine FPGA and Radio Frequency module(AD9361) to finish SDR platform. In this thesis, we design baseband receiver for demodulation and Decoder DVB-T signal. This baseband receiver needs the digital signal processing units which are down sampling, time synchronizer, frequency synchronizer, Fast Fourier Transform processor, channel estimator, channel equalizer, symbol de-interleaver, soft decision, bit de-interleaver, Viterbi decoder, packet synchronizer, outer de-interleaver, Reed Solomon decoder, de-scrambler. The signal which is under demodulation and decoder is MPEG-2 Transport Stream, and we can play the video via VLC player.
First, we record DVB-T signal on Matlab and demodulate the signal. Furthermore, we design baseband digital signal processing units by using Verilog hardware description language and verify with iSim. Then, the real-time hardware is implemented and verified with SDR platform. After it is under demodulation and decoder, we are able to get MPEG-2 Transport Stream. We could play this Transport Stream to verify baseband receiver’s result.

中文摘要 i
ABSTRACT ii
謝誌 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1研究動機與背景 1
1.2 章節提要 2
第二章 數位電視地面廣播規格簡介 3
2-1 正交分頻多工系統簡介 3
2-1-1 正交分頻多工系統簡介 3
2-1-2 保衛區間(Guard Interval, GI) 6
2-2 DVB-T系統規格及簡介 8
2-2-1 DVB-T傳輸模式 8
2-2-2 DVB-T系統規格 9
2-3 DVB-T的通道編碼 11
2-4 OFDM訊框架購 19
第三章 數位電視地面廣播接收系統基頻處理流程 22
3-1 降頻取樣 23
3-1-1 反贋頻濾波器 23
3-1-2 降取M倍 23
3-2 時間同步 24
3-2-1 時間同步偏移 24
3-2-2 時間同步原理 25
3-3 頻率同步 26
3-3-1 小數倍頻率誤差估測 27
3-3-2 整數倍頻率誤差估測 28
3-4 快速傅立葉轉換 29
3-4-1 Radix-22-DIF演算法原理 30
3-4-2 位元反轉排序 31
3-5 解訊框架構 31
3-5-1 次訊框同步 31
3-5-2 解訊框資訊 32
3-6 通道估測及等化 32
3-6-1 通道估測 32
3-6-2 線性內插 33
3-6-3 通道等化 34
3-7 內部解交錯器 35
3-7-1 符元解交錯器 35
3-7-2 位元解交錯器 37
3-8 軟式決策器 38
3-9 封包同步器 47
3-10 外部解交錯器 48
3-11 解亂碼器 49
第四章 數位電視地面廣播接收機硬體架構 50
4-1 整數倍頻率同步 50
4-2 符元解交錯器 52
4-3 軟式決策 54
4-3-1 以CORDIC實現通道狀態資訊之絕對值 55
4-4 位元解交錯器 60
4-5 封包同步 61
4-6 外部解交錯器 62
4-7 解亂碼器 64
第五章 軟體定義無線電平台實驗結果 65
5-1 軟體定義無線電 65
5-2 軟體定義無線電平台介紹 65
5-2-1 FPGA介紹 66
5-2-2 射頻模組及DVB-T全向性天線 67
5-2-3 AD9361參數操作 68
5-3 傳輸參數訊號 69
5-4 硬體解調量測實驗 71
5-4-1 硬體實錄量測 71
5-4-2 通道狀態資訊效能分析 74
5-4-3 合成報告書 75
5-5 硬體解調解碼成果 76
第六章 結論 77
參考文獻 78

[1] ETSI EN 300 744, Digital Video Broadcasting(DVB), Framing structure channel coding and modulation for digital terrestrial television. European Standard.
[2] R. Andraka, "A survey of CORDIC algorithms for FPGAs, " Proc. ACM/SIGDA Conf., pp.191 1998.
[3] C.H. Kuo, “Design and Implementation of Viterbi Decoder for Multi-Rate Convolutional Code in DVB-T System, ” National Central University, Master’s thesis, Jul. 2010.
[4] W.Y. Huang, “Design and FPGA Implementation of An Improved Inter-Carrier Interference Mitigation Scheme for OFDM System in High-Mobility Environment, ” National Central University, Master’s thesis, 2010.
[5] W.H. Tsai, “implement MPEG-2 multiplexer system on DVB-T, ” National Central University, Master’s thesis, Jul. 2007.
[6] F.S. Huang, “Design and Implementation of Synchronization System for DVB-T Receiver, ” National Central University, Master’s thesis, Jul. 2006.
[7] J. Song, Z. Yang, L. Yang, K. Gong, C. Pan, J. Wang and Y. Wu, "Technical review on Chinese digital terrestrial television broadcasting standard and measurements on some working modes," IEEE Trans. on Broadcasting, vol. 53, pp. 1-7, Mar. 2007.
[8] Y.M. Chen, I.Y. Kuo, “Design of lowpass filter for digital down converter in OFDM receivers, ” International Conference on Wireless Networks, Comm. and Mobile Computing, vol. 2, pp. 1094-1099, Hawaii, USA, Jun. 2005.
[9] Y.M. Chen, “Design of Digital Front-End for OFDM Receivers with Asynchronous IF Sampling“, IEEE APWCS, Korea, 2006.
[10] E.R. Berlekamp, “Bit-Serial Reed-Solomon Encoders, ”IEEE Trans. Inform. Theory, vol. IT-28, no. 6, pp. 869-874, Nov.1982.
[11] H.M. Shao, T.k. Truong, L.J. Deutsch, J.H.Yuen, and I.S. Reed, “A VLSI Design of a Pipeline Reed-Solomon Decoder, ”IEEE Tran. On Computers, vol. C-34, no. 5, pp. 393-402, May 1985.
[12] J.E.Volder,“The cordic trigonometric computing technique,” IRE Transactions on Electronic Computers, vol. EC-8, no. 3, pp. 330 –334, Sept.1959.
[13] 賴柏洲 and 林世欽,數位電視技術原理. 全華圖書,2014.