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研究生:聶慈筠
研究生(外文):Tzu-Yun Nieh
論文名稱:P型複晶矽鰭式電晶體應用於電阻式記憶體(RRAM)之性能與可靠度研究
論文名稱(外文):Investigation on the Performance and Reliability of P-type Poly-Si FinFETs Applied to Resistance Random Access Memory(RRAM)
指導教授:曾百亨曾百亨引用關係
指導教授(外文):Bae-Heng Tseng
學位類別:碩士
校院名稱:國立中山大學
系所名稱:材料與光電科學學系研究所
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:111
中文關鍵詞:電阻式記憶體低溫多晶矽閘極引致汲極漏電、交流電應力鰭式電晶體
外文關鍵詞:GIDLAC StressFinFETsRRAMLTPS
相關次數:
  • 被引用被引用:2
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近幾年由於科技的進步,資訊的取得和儲存成本大幅下降,造成全球資料 量急速攀升,如何儲存和快速分析大量的數據便成為新的研究重點,目前三個被視為最有前景的技術分別是高速運算、大數據 (Big data)及物聯網(Internet of Things IoT),這些技術都仰賴於記憶元件的革新。目前非揮發性記憶體因具有不供電仍具備存取信息的能力,故市占率已達到將近100%,但因其存取速度緩慢而有發展次世代記憶體的必要性,次世代記憶 體兼具節能、存取速度快與大容量等優點,其中尤以電阻式記憶體(RRAM)具有低功耗與高性能的特性,且其製程可與CMOS邏輯製程相容,因此被視為下一世代記憶體中最具發展潛力的項目。
RRAM操作時阻值的切換分為高阻態(HRS)與低阻態(LRS),而將RRAM做 成一個晶片陣列化後,便會出現因電路電阻高低分佈產生「潛行電流」的問題 ,造成誤判阻值的情形,而使用電晶體串聯電阻式記憶體(1T1R)為解決此問題最為常見的方法。本論文將對1T1R元件結構下因串聯電晶體對HRS造成的影響進行研究,計畫以提升電晶體施加的閘極電壓進而減少對RRAM抹除過程中電阻分佈的影響。於量測電阻式記憶體所串聯之低溫多晶矽鰭式電晶體時,發現於電晶體關態時出現異常漏電現象,進行變溫及變電場實驗探討漏電量與其關連性。而RRAM最佳Reset條件為使用AC電壓以短升壓時間與長降壓時間可達最佳Reset效果,故對低溫多晶矽鰭式電晶體於交流負偏壓電應力下之性能與可靠度進行研究,欲求得1T1R元件最佳Reset條件之交流電壓波形。
Several promising technologies such as high-speed computing, big data and IoT depend on the innovation of memory devices. The non-volatile memory can access information without power supply. However, its access speed is slow that it’s necessary to develop the next-generation memory. The merits of next generation of memory are energy saving, fast access speed and large capacity. Among them, Resistive Random Access Memory (RRAM) is regarded as the most potential next generation memory.
The resistance switching of RRAM could be divided into high resistance state (HRS) and low resistance state (LRS). In addition, RRAM has the issue of "sneak current" owing to resistance variation, which causes the misjudgment. To improve the performance, one RRAM integrated with one transistor (1T1R) is widely used.
Moreover, the distribution of high and low resistance during the RRAM operation is an urgent issue. This research will investigate the effect of transistor on HRS in 1T1R device. And it plans to increase the gate voltage which applied to the transistor and thereby reduce the effect on the resistance distribution during RRAM reset process.
Measuring the Low-Temperature Poly-Si (LTPS) Fin-Field-Effect-Transistor (FinFETs¬) in which the RRAM is connected in series, it is found that abnormal leakage occurs when the transistor is operated in off-state. By changing temperature/ electric field experiments to investigate the correlation of this leakage current. Generally, the optimal Reset condition of RRAM is applying AC voltage with short rising time and long falling time. As a result, the performance and reliability of LTPS-FinFET under AC negative bias stress are studied to obtain the best Reset condition of AC voltage waveform of the 1T1R device.
摘要 i
Abstract ii
圖目錄 vi
表目錄 xi
第一章 序論 1
1.1 前言 1
1.2 研究動機與目的 2
第二章 文獻回顧 3
2.1 關於記憶體 3
2.2 主要記憶體 4
2.2.1 動態隨機存取記憶體 4
2.2.2 靜態隨機存取記憶體 4
2.2.3 快閃記憶體 7
2.3 次世代記憶體 12
2.3.1 磁阻式記憶體 12
2.3.2 相變化記憶體 13
2.3.3 電阻式記憶體 14
2.4 絕緣層傳導機制 17
2.4.1 歐姆傳導(Ohmic Conduction) 18
2.4.2 蕭特基發射(Schottky Emission) 19
2.4.3 普爾-法蘭克發射(Poole-Frenkel Emission) 20
2.4.4 跳躍傳導(Hopping Conduction) 22
2.4.5 穿隧(Tunneling) 23
2.4.6 空間電荷限制電流(Space Charge Limited Current, SCLC) 24
2.5 關於電晶體 25
2.5.1 絕緣層上矽(Silicon On Insulator, SOI) 27
2.5.2 High-k 氧化層與金屬閘極 29
2.5.3鰭式場效電晶體(Fin Field-Effect Transistor, FinFETS) 32
2.5.4 低溫多晶矽 35
2.6 閘極引發汲極漏電 36
第三章 實驗及分析方法與儀器介紹 37
3.1 實驗儀器 37
3.1.1 多靶磁控濺鍍系統(Multi-Target Sputter) 37
3.1.2 N&K薄膜特性分析儀(N&K Analyzer) 37
3.1.3 精密半導體參數量測分析儀(Precision Semiconductor Parameter Analyzer) 39
3.2 實驗及量測方法 42
3.2.1 1T1R 元件 42
3.2.2 1T1R 元件電性量測方式 42
3.3電晶體元件參數萃取方式 43
3.3.1臨界電壓(Threshold Voltage, VT) 44
3.3.2次臨界擺幅(Subthreshold Swing, S.S) 45
3.3.3載子遷移率(Carrier Mobility, ) 46
第四章 實驗結果與討論 47
4.1 1T1R HRS電阻分佈之研究 47
4.1.1 實驗動機 47
4.1.2 NMOS 1T1R元件基本特性 49
4.1.3 NMOS 1T1R元件電性量測結果分析 52
圖4-16 電阻值分布標準差與Reset電壓關係圖 57
4.1.4 PMOS 1T1R元件基本特性 58
4.1.5 PMOS 1T1R元件電性量測結果分析 61
4.2 多晶矽鰭式場效電晶體異常漏電流之研究 63
4.2.1 實驗動機 63
4.2.2 元件基本特性 64
4.2.3 PMOS電晶體關態電壓異常之分析 66
4.3 多晶矽鰭式場效電晶體於交流電應力下劣化之研究 80
4.3.1 實驗動機 80
圖4-49 RRAM最佳Reset條件示意圖 80
4.3.3 LTPS FinFETs 於直流電應力與交流電應力下之劣化 81
4.3.4 LTPS FinFETs 於交流電應力不同脈衝波形下之劣化 85
第五章 結論 92
參考文獻 94
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