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研究生:蔡修群
研究生(外文):Hsiu-Chun Tsai
論文名稱:高壓雙向電流偵測器與低功率延遲乘積之單端讀寫無擾動式6T靜態隨機存取記憶體
論文名稱(外文):A High Voltage Bidirectional Current Sensor and A Single-ended Disturb-free 6T SRAM with Low Power-Delay Product
指導教授:王朝欽
指導教授(外文):Chua-Chin Wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
中文關鍵詞:讀取穩定度漏電流電流偵測器電池管理系統靜態隨機存取記憶體
外文關鍵詞:read stabilitycurrent sensorleakage currentbattery management systemstatic random access memory
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本論文包含兩個研究主題, 第一個主題為高壓雙向電流偵測器, 使用TSMC 0.50 m CMOS High Voltage Mixed Signal Based LDMOS AI_USG Polycide2P3M (T50UHV) 製程實現,以驗證設計原理。第二個主題為具降低讀取延遲乘積的單端讀寫無擾動式6T 靜態隨機存取記憶體,並使用TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V (TN40G) 製程實現,以驗證在漏電流較大的先進CMOS 製程中,此架構之SRAM 資料的穩定性。
前述第一個主題為針對水下載具電池系統的電流偵測控制晶片,係偵測電池組內電池的電流狀態,利用電流鏡與比較器來偵測電流流向,達到判別電池充放電狀態之目的,並且以T 型正反器來控制開關,以得到較精準的電流偵測,提供管理系統之管理使用。模擬結果可操作於電壓8 V 20 V,且誤差在0.85 % 以內。
前述第二個主題係以本實驗室先前文獻提出之單端讀寫無擾動式5T 靜態隨機存取記憶體進行改良,係為了解決其記憶體單元受漏電流影響,以致在長時間讀取資料時,儲存點資料隨著漏電流電荷累積而發生錯誤轉態。本論文於原先之架構下加入一NMOS 電晶體,以提供記憶體單元漏電流路徑,避免漏電流電荷在儲存點累積,而破壞記憶體資料,並且改善先前文獻提出之降低功率延遲乘積電路,模擬結果平均功率延遲乘積能量消耗降低11.41 %,記憶體每次存取功率消耗為0.306 pJ。

關鍵詞:電流偵測器、電池管理系統、靜態隨機存取記憶體、漏電流、讀取穩定度
This thesis investigates two research topics, including a high voltage bidirectional current sensor and a low power SRAM design. The current sensor was realized by TSMC 0.50 m CMOS High Voltage Mixed Signal Based LDMOS AI_USG Polycide 2P3M (T50UHV) Process to justify the expected accuracy of current detection. The singleended disturb-free 6T SRAM demonstrated in the second topic is realized by TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V (TN40G) Process to enhance the stability which would be severely affected by the large leakage current in deep sub-micro CMOS technologies.
The HV current sensor was designed monitor the battery current such that it is able to be applied in battery management systems. By taking advantage of a current mirror and a comparator to sense the current direction such that the charging or discharging status can
be decided. Moreover, a T flip-flop is used to control a switch to achieve more precise current sensing. The simulation results show that the input voltage range of the battery string is from 8 V to 20 V and the sensing error is better than 0.85 %.
The second topic means to improve the single-ended disturb-free SRAM developed by our laboratory. To avoid data hazard caused by leakage current when the memory cell in the read mode, an NMOS transistor is added at the foot to drain a leakage current path to isolate the data state in memory cell from noise. Moreover, the simulation results of average power-delay product (PDP) is improved by 11.41 % and the energy/access is 0.306 pJ.

Keyword: current sensor, battery management system, static random access memory, leakage current, read stability
論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
1 概論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 相關文獻與研究探討. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 電阻型電流偵測. . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 濾波器型電流偵測. . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.3 感測電壓放大型電流偵測. . . . . . . . . . . . . . . . . . . . 7
1.2.4 電流映射型電流偵測. . . . . . . . . . . . . . . . . . . . . . . 8
1.2.5 靜態隨機存取記憶體單元. . . . . . . . . . . . . . . . . . . . 9
1.2.6 記憶體單元輔助電路. . . . . . . . . . . . . . . . . . . . . . . 10
1.3 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.1 高壓雙向電流偵測器. . . . . . . . . . . . . . . . . . . . . . . 12
1.3.2 靜態隨機存取記憶體. . . . . . . . . . . . . . . . . . . . . . . 12
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 高壓雙向電流偵測器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 高壓雙向電流偵測器架構. . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 高壓雙向電流偵測器電路設計. . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 雜訊濾波器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.2 偵測級. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.3 控制器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 晶片佈局. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 預計規格與電路模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.1 電路模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.2 預計規格列表與文獻比較. . . . . . . . . . . . . . . . . . . . 22
2.6 晶片量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6.1 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6.2 量測結果與分析. . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.7 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 低功率延遲乘積之單端讀寫無擾動式
6T 靜態隨機存取記憶體. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 低功率延遲乘積之6T 記憶體電路架構. . . . . . . . . . . . . . . . . 29
3.3 低功率延遲乘積之6T 記憶體電路設計. . . . . . . . . . . . . . . . . 31
3.3.1 單端讀寫無擾動式6T 記憶體單元. . . . . . . . . . . . . . . . 31
3.3.2 行解碼器與列解碼器. . . . . . . . . . . . . . . . . . . . . . . 32
3.3.3 SRAM 控制電路. . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.4 共享式記憶體單元. . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.5 降低功率延遲乘積輔助電路. . . . . . . . . . . . . . . . . . . 35
3.3.6 內建自我測試電路. . . . . . . . . . . . . . . . . . . . . . . . 38
3.4 晶片佈局. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.5 佈局後模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.1 記憶體單元模擬結果. . . . . . . . . . . . . . . . . . . . . . . 41
3.5.2 整體記憶體電路模擬. . . . . . . . . . . . . . . . . . . . . . . 43
3.5.3 模擬結果與文獻比較. . . . . . . . . . . . . . . . . . . . . . . 47
3.6 晶片量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.6.1 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.6.2 量測結果與分析. . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4 結論與未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.1 研究成果與結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2 未來研究規劃. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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