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研究生:陳皇任
研究生(外文):Chen, Huang-Jen
論文名稱:鰭式電晶體之抑制閘極漏電流與提升閘極介電層可靠度研究
論文名稱(外文):Suppressed Gate Leakage Current and Enhanced Gate Dielectric Reliability in FinFET
指導教授:張廖貴術
指導教授(外文):ChangLiao, Kuei-Shu
口試委員:趙天生吳永俊
口試委員(外文):Chao, Tien-ShengWu, Yung-Chun
口試日期:2018-09-21
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:107
語文別:中文
論文頁數:80
中文關鍵詞:鰭式電晶體閘極介電層閘極漏電流可靠度
外文關鍵詞:FinFETGate dielectricGate leakage currentReliability
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隨著元件特徵尺寸微縮,過薄氧化層所產生的問題開始受到重視,本論文研究之重點為鰭式電晶體之閘極漏電流與氧化層可靠度,三個與閘極堆疊相關的實驗如下:第一,在閘極堆疊之不同位置加入極低能量氟離子佈植製程以鈍化介電層中的氧化層陷阱電荷;第二,在二氧化鉿沉積前及後進行低溫氨氣退火以增加二氧化鉿之熱穩定性;第三,多鈦氮化鈦取代氮化鈦的不同部分以增加脫附氧化層及擴散阻擋層的效果。
第一部份,在閘極堆疊之二氧化矽介面層上、二氧化鉿介電層上、氮化鈦薄膜上加入極低能量氟離子佈植製程。在二氧化鉿與氮化鈦沉積後進行氟離子佈值可以減少閘極漏電流並提升氧化層可靠度,推測氧化層陷阱電荷被鈍化。除此之外,氟離子佈植對於導通電流、關閉狀態電流、臨界電壓、次臨界擺幅、轉導之影響很小,推測因為氟離子佈植製程之劑量較小,所以對元件之電特性影響不大。
第二部分,在二氧化鉿沉積前及後進行不同持溫時間之低溫氨氣環境退火。在二氧化鉿沉積後進行氨氣退火之樣品有較低之閘極漏電流,推測為二氧化鉿之晶粒邊界減少,然而,二氧化鉿沉積前氨氣退火15秒和二氧化鉿沉積後氨氣退火60秒樣品之F-N stress後臨界電壓位移更為嚴重,此原因可能為過度之氮化產生介面缺陷,使氧化層可靠度惡化。經過氨氣退火之樣品的閘極電容值些微提升,推測為氮氧化鉿(HfON)和氮氧化矽(SiON)之相對介電係數較二氧化鉿和二氧化矽還高。
第三部分,多鈦氮化鈦取代氮化鈦薄膜的底部、中部以及全部。實驗片之臨界電壓皆往負方向位移,此原因為較高之鈦/氮比使功函數降低。使用多鈦氮化鈦之樣品有較高之導通電流與閘極電容,可歸功於多鈦氮化鈦有更強之脫附介面層效果。閘極漏電流和氧化層可靠度亦有提升,推測為氮化鈦之柱狀晶粒邊界產生氧填充效應,使金屬與氧化層/矽基板有較少之交互擴散。
With the shrinking feature size of FinFET, the problem of ultrathin gate oxide is a growing concern. Gate leakage current and gate dielectric reliability of FinFET are investigated in this thesis. Three process experiments for gate stacks are performed as follows. First, ultralow-energy fluorine ion-implantation is employed at various positions of gate stacks to passivate oxide traps in gate dielectric. Second, NH3 annealing at low-temperature is applied before and after HfO2 gate dielectric deposition to enhance the thermal stability of HfO2. Third, Ti-rich TiN is used to replace conventional TiN at different depth of metal gate for enhancing interfacial layer (IL) scavenging and diffusion barrier property.
In the first part, fluorine ion-implantation at ultralow-energy is employed on SiO2 interfacial layer, HfO2 gate dielectric, or TiN cap, respectively. Suppressed gate leakage current and enhanced oxide reliability can be obtained with fluorine ion implantation after HfO2 and TiN deposition. This indicates that the oxide traps are passivated by fluorine ion. Effects of fluorine ion implantation on drive current, off current, threshold voltage, subthreshold swing, and transconductance are minor. This may be because low implantation dose may not affect the electrical characteristics.
In the second part, NH3 annealing at low-temperature is applied before and after HfO2 gate dielectric deposition with different soaking time. The gate leakage current can be suppressed by performing NH3 annealing after HfO2 deposition. The results indicates that grain boundaries of HfO2 are reduced. However, threshold voltage shift after F-N stress is increased in sample with 15 seconds NH3 annealing before HfO2 deposition and sample with 60 seconds NH3 annealing after HfO2 deposition. It is suggested that interface defects may be induced by over nitridation, resulting in degraded gate dielectric reliability. Devices with NH3 annealing show slightly increased gate capacitance, which can be referred to higher κ-values of HfON and SiON than that of HfO2 and SiO2.
In the third part, Ti-rich TiN is used to replace the bottom, middle, or entire parts of conventional TiN, respectively. Negative threshold voltage shifts are seen in all samples, indicating lower work function of Ti-rich TiN due to the increased Ti/N ratio. The on current and gate capacitance can be enhanced in Ti-rich TiN samples, which can be attributed to stronger IL scavenging effect. Also, gate leakage current and oxide reliability are improved. This may be due to the oxygen incorporation effect at the columnar grain boundaries of TiN, resulting in less inter-diffusion between metal and oxide/Si.
摘要 i
Abstract ii
致謝 iv
目錄 v
圖目錄 vii
表目錄 x
第一章 序論 1
1.1 前言 1
1.2 電晶體尺寸微縮 1
1.3 鰭式電晶體 1
1.4 氧化層微縮及其產生之影響 2
1.5 氟於閘極氧化層之效應 2
1.6 二氧化鉿介電氧化層之氮化 3
1.7 氮化鈦薄膜之氮、鈦比例調變 4
1.8 論文架構 5
第二章 元件製程與量測 21
2.1 鰭式電晶體製造流程 21
2.1.1 鰭式電晶體標準製程 21
2.1.2 本論文研究製程 21
2.2 電晶體電性量測 22
2.2.1 電容量測 22
2.2.2 基礎電性量測 22
2.2.3 可靠度量測 23
第三章 低能量氟離子佈植於閘極堆疊之電特性研究 25
3.1 研究動機 25
3.2 製程與量測 26
3.2.1 製程條件 26
3.2.2 量測參數 27
3.3 結果與討論 27
3.4 結論 30
第四章 閘極介電質氨氣退火處理之電特性研究 43
4.1 研究動機 43
4.2 製程與量測 44
4.2.1 製程條件 44
4.2.2 量測參數 45
4.3 結果與討論 45
4.4 結論 47
第五章 複合結構氮化鈦薄膜之電特性研究 59
5.1 研究動機 59
5.2 製程與量測 61
5.2.1 製程條件 61
5.2.2 量測參數 61
5.3 結果與討論 61
5.4 結論 63
第六章 結論與未來展望 75
6.1 結論 75
6.2 未來展望 76
參考文獻 78
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