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研究生:周祐安
研究生(外文):Chou, You-An.
論文名稱:一個資料率為每秒兩百五十億位元之資料與時脈恢復電路設計
論文名稱(外文):A 25Gb/s clock and data recovery circuit design
指導教授:盧志文盧志文引用關係
指導教授(外文):Lu, Chih-Wen
口試委員:李泰興尹炳業
口試委員(外文):Lee, Tai-HsingYin, Ping-Yeh
口試日期:2019-01-28
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:85
中文關鍵詞:乙太網路時脈與資料恢復電路二位元式相位偵測器壓控震盪器除頻器
外文關鍵詞:EthernetCDRBBPDVCOFD
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隨著通訊技術的逐年演進,新的應用對於即時傳輸巨量數據的能力也越發的要求,資料傳輸率的成長速度幾乎以每五年十倍的速率不斷的進步。以乙太網路(Ethernet)為例,從早期僅具有每秒十兆位元(10Mbps)之資料傳輸率到現在已經到達每秒十吉位元(10Gbps)的資料傳輸率,甚至還在制定中的一百吉位元(100Gbps)之乙太網路,時脈與資料恢復電路(Clock and Data Recovery, CDR)在通訊系統速度的演進上扮演著重要的角色。
本論文旨在提出一個具有每秒二十五吉位元(25Gbps)資料傳輸率的時脈與資料恢復電路(Clock and Data Recovery, CDR)設計,此電路將著眼於未來一百吉位元之乙太網路系統的應用來設計,此系統將分為四路,每路以二十五吉位元之資料傳輸率為基礎做設計。論文中介紹過去到現在時脈與資料恢復電路的演進,以及此電路設計時應用上的考量,從系統架構說明到類比部份的電路模擬再到射頻部份之電磁模擬,詳細內容將在論文中一一討論。電路設計上使用了半速率的二位元相位偵測器(Bang-Bang Phase Detector, BBPD),相較於線性相位偵測器(Linear Type Phase Detector),當操作頻率超過1GHz時不會有線性區間的問題。並且使用了半速率相差九十度相位差之差動時脈訊號來對輸入之不歸零(Non-Return-to-Zero, NRZ)訊號做取樣,除了能獲取相位資訊外,當相位鎖上時,時脈與資料恢復電路同時也能對輸入的不歸零訊號進行解雙工的處裡。
壓控震盪器電路(Voltage Controlled Oscillator, VCO)以LC-tank架構實現,使用頂端偏壓架構使得輸出時脈訊號的偏壓位於電源電壓(Power Supply Voltage)的一半,使得頻率變化範圍能夠最大化。最後除頻器電路(Frequency Divider, FD)則使用了電流模態邏輯閂來實現,兩組電流模態邏輯透過相互鎖定產生九十度相位差的時脈訊號,自振頻設計為12.5GHz,經過一級緩衝器後傳到相位偵測器。
本論文的時脈與資料恢復電路採用TSMC 90 nm 1P9M製程實現。壓控震盪器的中心頻率設計為25GHz,透過除頻器產生半速率且相差九十度之時脈訊號來對資料做取樣而產生領先或落後的資訊,透過一比較周期內做兩次領先或落後的比較,此電路具有較佳的相位偵測功能,輸出資料之資料率為12.5Gbps於相位鎖定時具有0.85ps(rms)的邊緣抖動範圍。此電路的操作電壓為1.2V,功耗為67.6mW,晶片尺寸包含PAD為0.777 mm2。
With the ever-growing communication technology, the more demands on the ability of transferring huge amount of data in a limited period in new applications. The progress of data transfer rate grows up with the speed of almost 10 times per 5 years. Take Ethernet for example, in the beginning the data transfer rate is only 10Mbps but now already grown up to 10Gbps, even the future 100Gbps Ethernet, which is under establish, the clock and data recovery circuits still play an important role in the progress of data transfer rate in communication systems.
This thesis aims to propose a clock and data recovery circuit with the data rate of 25Gbps, which is designed to be used in the future 100Gbps Ethernet system. The 100Gbps system is designed to be divided into four channels, each channel operates in 25Gbps data rate. The dissertation will introduce the evolution of clock and data recovery circuit and considerations including the system blocks operation and analog circuit techniques and even electrical-magnetic simulation of radio frequency circuit that should be taken into in the design of such circuits, all the topics will be discussed in the following contents. The architecture of phase detector is half-rate, Bang-Bang type, compared to the linear type counterpart, which avoids the linear range problem when the operation frequency is over 1GHz.With the input NRZ data sampled by the half-rate quarter phase differential clock signal, not only the phase information of lead or lag can be obtained but also the input data can be demutiplexed by quarter phase clock signal when the phase is locked.
The voltage controlled oscillator is realized with LC-tank architecture, with top-biased topology, the common mode voltage of the output clock signal can be half of the power supply voltage, which makes the most output frequency tuning range. Finally, the current mode logic is applied in the frequency divider circuit to make the self-oscillating frequency at 12.5GHz, the quarter phase is generated because two current mode logic latches lock each other. After passing through one-stage current mode logic buffer, the half-rate clock signal is applied to the phase detector.
This clock and data recovery circuit is realized by TSMC 90 nm 1P9M process. The center frequency of voltage controlled oscillator is designed in 25GHz, followed by frequency divider half-rate quarter phase clock signal is produced and can be used to sample input NRZ data to detect phase information. Since there are two phase detection within one comparison period, this circuit has better phase detection ability compared to ordinary counterpart. The output data rate is 12.5Gbps. When the phase is locked, the output data jitter is 0.85ps, rms. The supply voltage is 1.2 volte, power dissipation is 67.6 mW in simulation, the layout size is 0.777 m2 including PAD.
中文摘要
目錄
圖目錄
表目錄
第一章 簡介 13
第二章 時脈與資料恢復電路 16
第三章 電路設計與模擬 39
第四章 模擬結果 57
第五章 量測環境與結果 69
第六章 結論與未來展望 82
參考文獻 84
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[8] Samuel Palermo, “Texas A&M_Sam Palermo_High speed Links
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[11] J. Lee and B. Razavi, “A 40-Gb/s clock and data recovery
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