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研究生:洪傳奇
研究生(外文):Hung, Chuan-Chi
論文名稱:24 GHz與38 GHz功率放大器及線性化技術研究
論文名稱(外文):Research on 24 GHz and 38 GHz Power Amplifiers and Linearization Techniques
指導教授:蔡政翰蔡政翰引用關係
指導教授(外文):Tsai, Jeng-Han
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:219
中文關鍵詞:互補式金屬氧化物半導體功率放大器變壓器線性器功率結合技術電流結合技術38 GHzK頻帶
外文關鍵詞:CMOSpower amplifierstransformerlinearizerpower combining techniquescurrent combining techniques38 GHzK band
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第一顆電路為利用直接匹配技術之38 GHz二級功率放大器,透過傳輸線匹配網路達成輸出功率阻抗匹配、輸入共軛匹配之效果。當操作頻率為38 GHz且功率放大器的VG與VDD為-0.5 V與4 V時,其功率增益(Power gain)約為15.63 dB,飽和輸出功率Psat約為20.31 dBm,1-dB增益壓縮點之輸出功率(OP1dB)約為18.9 dBm,靜態電流約為81.5 mA,最大功率附加效率Peak PAE約為23.8 %,整體晶片佈局面積為1.2 mm × 0.8 mm。
第二顆電路為內具線性器之38 GHz二級功率放大器,線性器架構採用共源極組態。當操作頻率為38 GHz且VG為-0.5 V時,在線性器開啟狀態下(Vctrl = -0.2 V),量測小訊號增益(S21)約為12.61 dB,輸入輸出反射損耗(S11、S22)分別為-7.81 dB與-13.23 dB,三階交互調變失真IMD3在-40 dBc的輸出功率約為14.12 dBm,整體晶片佈局面積為1.2 mm × 0.8 mm。
第三顆電路為內具線性器之38 GHz二級功率放大器,線性器架構採用共源極串級電阻組態。當操作頻率為38 GHz且VG為-0.5 V時,在線性器開啟狀態下(Vctrl = -0.3 V),量測小訊號增益(S21)約為12.43 dB,輸入輸出反射損耗(S11、S22)分別為-9.3 dB與-12.71 dB,三階交互調變失真IMD3在-40 dBc的輸出功率約為13.55 dBm,整體晶片佈局面積為1.2 mm × 0.8 mm。
第四顆電路為內具線性器之38 GHz二級功率放大器,線性器架構採用疊接組態。當操作頻率為38 GHz且VG為-0.5 V時,在線性器開啟狀態下(Vctrl = -0.4 V),量測小訊號增益(S21)約為11.56 dB,輸入輸出反射損耗(S11、S22)分別為-9.28 dB與-12.3 dB,三階交互調變失真IMD3在-40 dBc的輸出功率約為14.42 dBm,整體晶片佈局面積為1.2 mm × 0.8 mm。
第五顆電路為利用變壓器功率結合技術之38 GHz功率放大器,透過變壓器的功率結合與阻抗轉換特性來達成輸入共軛匹配與輸出功率匹配。當操作頻率為38 GHz且VG1為0.6 V時,功率增益(Power gain)約為15.07 dB,飽和輸出功率Psat約為19.98 dBm,1-dB增益壓縮點之輸出功率(OP1dB)約為15.05 dBm,靜態電流約為114 mA,最大功率附加效率Peak PAE約為29.42 %,整體晶片佈局面積為0.47 mm × 0.57 mm。
第六顆電路為利用變壓器電流結合技術之24 GHz功率放大器,採用二級功率放大器的方式以提升增益,接著使用變壓器電流結合技術來提高輸出功率。當操作頻率為24 GHz且VG1為1 V時,功率增益(Power gain)約為14.07 dB,飽和輸出功率Psat約為23.9 dBm,1-dB增益壓縮點之輸出功率(OP1dB)約為19.07 dBm,靜態電流約為354.06 mA,最大功率附加效率Peak PAE約為13 %,整體晶片佈局面積為0.99 mm × 0.91 mm。
The first circuit is a 38 GHz two stage power amplifier utilize transmission line matching network to achieve output matching and input impedance. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, the power amplifier exhibits the power gain of 15.63 dB, the saturated output power of 20.31 dBm, the output power of 18.9 dBm at 1-dB compression point, the quiescent current of approximately 81.5 mA and the maximum power added efficiency of approximately 23.8%. The chip size is 1.2 mm × 0.8 mm.
The second circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using common source configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.2 V), the power amplifier exhibits the small signal gain (S21) of approximately 12.61 dB, the input and output reflection coefficient (S11, S22) of -7.81 dB and -13.23 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 14.12 dBm. The chip size is 1.2 mm × 0.8 mm.
The third circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using common source cascade resistance configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.3 V), the power amplifier exhibits the small signal gain (S21) of approximately 12.43 dB, the input and output reflection coefficient (S11, S22) of -9.23 dB and -11.81 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 13.55 dBm. The chip size is 1.2 mm × 0.8 mm.
The fourth circuit is a 38 GHz two stage power amplifier with built-in linearizer, the frame of the linearizer is using cascode configuration. At 38 GHz and the VG and VDD of the power amplifier operate in -0.5 V and 4 V, when the linearizer is on (Vctrl = -0.4 V), the power amplifier exhibits the small signal gain (S21) of approximately 11.56 dB, the input and output reflection coefficient (S11, S22) of -9.28 dB and -12.3 dB, and the third-order intermodulation distortion (IMD3) can be maintained under -40 dBc when the output power less than 14.42 dBm. The chip size is 1.2 mm × 0.8 mm.
The fifth circuit is a 38 GHz power amplifier with transformer power combining technique. To achieve input impedance matching, output power matching, we utilize the transformer to implement the impedance conversion and the power combining. At 38 GHz and the VG1 of the power amplifier operate in 0.6 V, the power amplifier exhibits the power gain of 15.07 dB, the saturated output power of 19.98 dBm, the output power of 15.05 dBm at 1-dB compression point, the quiescent current of approximately 114 mA and the maximum power added efficiency of approximately 29.42 %. The chip size is 0.47 mm × 0.57 mm.
The last circuit is a 24 GHz power amplifier with transformer power combining technique and current combining technique. To achieve high output power, we utilize the current combining technique. At 24 GHz and the VG1 of the power amplifier operate in 1 V, the power amplifier exhibits the power gain of 18.07 dB, the saturated output power of 23.9 dBm, the output power of 19.07 dBm at 1-dB compression point, the quiescent current of approximately 354.06 mA and the maximum power added efficiency of approximately 13.63 %. The chip size is 0.99 mm × 0.91 mm.
摘要 I
ABSTRACT III
誌謝 VI
目錄 V11
圖目錄 XI
表目錄 XXII

第一章 緒論 1
1.1 研究背景與動機 1
1.2 文獻探討 1
1.3 研究成果 5
1.4 論文架構 7

第二章 功率放大器基本介紹 9
2.1 概述 9
2.2 功率放大器之重要設計參數 10
2.2.1 功率(Power) 10
2.2.2 線性度(Linearity) 11
2.2.3 效率(Efficiency) 15
2.3 功率放大器設計製程 15
2.3.1 砷化鎵製程之偏壓與電流分析 15
2.3.2 砷化鎵製程之增益與功率分析 17
2.3.3 CMOS製程之偏壓與電流分析 22
2.3.4 CMOS製程之增益與功率分析 23

第三章 38 GHz二級功率放大器設計 27
3.1 簡介 27
3.2 38 GHz二級功率放大器設計 28
3.2.1 偏壓分析與選擇 28
3.2.2 電晶體元件尺寸分析與選擇 30
3.2.3 匹配網路設計 32
3.2.4 旁路電路設計 35
3.3 功率放大器之模擬結果 38
3.4 功率放大器之量測結果 41
3.5 問題與討論 48
3.6 總結 51

第四章 內具線性器之38 GHz二級功率放大器設計 53
4.1 簡介 54
4.2 內具線性器之38 GHz二級功率放大器設計 54
4.2.1 線性器原理簡介 54
4.2.2 具內建線性器功率放大器之增益分析 56
4.2.3 線性器架構選擇 57
4.3 內具共源極組態線性器之功率放大器 59
4.3.1 功率放大器模擬結果 59
4.3.2 功率放大器之量測結果 62
4.4 內具共源極組串級電阻組態線性器之功率放大器 69
4.4.1 功率放大器之模擬結果 69
4.4.2 功率放大器之量測結果 72
4.5 內具疊接組態線性器之功率放大器 79
4.5.1 功率放大器之模擬結果 79
4.5.2 功率放大器之量測結果 82
4.6 問題與討論 89
4.7 總結 94

第五章 38GHz Half-turn變壓器功率合成技術之功率放大器 97
5.1 簡介 97
5.2 38GHz Half-turn變壓器功率合成技術之功率放大器設計 99
5.2.1 偏壓分析與選擇 99
5.2.2 功率放大器組態選擇 101
5.2.3 電晶體尺寸分析與選擇 102
5.2.4 變壓器原理 108
5.2.5 輸出匹配網路設計 109
5.2.6 輸入匹配網路設計 118
5.2.7 旁路電路設計 125
5.3 功率放大器之模擬結果 128
5.4 功率放大器之量測結果 134
5.5 問題與討論 148
5.6 總結 150

第六章 變壓器電流結合技術之24 GHz功率放大器 153
6.1 簡介 153
6.2 變壓器電流合成技術之24 GHz功率放大器設計 154
6.2.1 偏壓分析與選擇 154
6.2.2 組態選擇 156
6.2.3 電晶體尺寸分析與選擇 157
6.2.4 輸出匹配網路設計 161
6.2.5 輸入匹配網路設計 167
6.2.6 旁路電容設計 174
6.2.7 變壓器電流合成技術 177
6.2.8 驅動級設計 179
6.2.9 級間匹配網路設計 187
6.2.10 輸出端變壓器電流合成設計 188
6.2.11 輸入端變壓器電流合成設計 195
6.3 功率放大器之模擬結果 202
6.4 功率放大器之量測結果 206
6.5 總結 209

第七章 結論 211

參考文獻 215

自傳 219
學術成就 219
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