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研究生:彭柏維
研究生(外文):Peng, Bo-Wei
論文名稱:應用於高頻與高壓電路之靜電放電防護設計
論文名稱(外文):ESD Protection Designs for High-Frequency and High-Voltage Applications
指導教授:林群祐林群祐引用關係
指導教授(外文):Lin, Chun-Yu
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:英文
論文頁數:145
中文關鍵詞:二極體靜電放電高頻高壓低損耗寄生電容
外文關鍵詞:Dual-diodeElectrostatic discharge (ESDhigh-frequencyhigh-voltagelow-lossparasitic capacitance
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為了避免積體電路遭受靜電放電的破壞,靜電放電防護元件通常被設計在電路的輸入/輸出端。操作在順偏條件的二極體適合被作為靜電放電防護元件,因此靜電放電防護二極體被廣泛應用在高頻以及高壓電路,然而靜電放電防護二極體的寄生電容卻嚴重地影響電路的高頻特性,導致信號不斷流失,為了解決信號損失的問題,靜電放電防護二極體的寄生電容必須被最小化。然而,防護元件的寄生電容能夠縮小的範圍仍然有限,一個元件同時擁有足夠的靜電放電防護能力以及小的寄生電容是相當困難的。因此,本論文提出一種低損耗焊墊的結構,能夠有效降低防護元件對高頻的影響,透過LC共振原理使K/Ka-bands中的信號損失降至最低。低損耗焊墊搭配靜電放電防護雙二極體已被實現在0.18μm互補式金氧半製程中,從高頻量測中證實,所提出之結構的信號損失較傳統結構低了六至十倍。最後,藉由各項靜電放電耐受度測試驗證,所提出之結構能夠擁有足夠高的靜電放電防護能力。
由於二極體為單向導通元件,僅適合提供一個靜電放電的路徑,需額外加入靜電放電箝制電路才能提供電路完整的防護,然而靜電放電電流透過靜電放電箝制電路排放,通常需要較遠的距離。因此,本論文提出一種雙向導通的P型二極體結構,藉由PN接面的空乏區控制其通道,當靜電放電事件發生時,通道的空乏區將消失並排放靜電電流,而在正常工作中,空乏區應切斷其通道並有足夠低的漏電流,在高壓的應用中,橫向雙擴散電晶體經常被作為靜電放電防護元件,然而橫向雙擴散電晶體的結構複雜且不易設計,使得高壓操作中的靜電放電防護設計受到挑戰。二極體不但結構簡單且有足夠的靜電放電耐受度,因此本論文針對二極體的結構去進行改良,所提出的P型空乏二極體已被實現在0.50μm互補式金氧半製程中。從直流量測結果證實,在正常工作下P型空乏二極體有足夠低的漏電流,靜電放電耐受度測試中,透過通道排放靜電電流的想法是可行的但仍有需改進的地方。最後一章節的未來工作中將會提及一些改良的結構與想法。
The electrostatic discharge (ESD) protection devices are generally designed and employed near the input/output (I/O) pad to avoid the impact of ESD events. The diode operated under forward-biased condition is widely used as an ESD protection device in the integrated circuits (ICs). However, the parasitic capacitance of ESD protection diode seriously affects the high-frequency characteristics of the circuit and causes the signal to be lost. In order to solve the problem of signal loss, the parasitic capacitance of ESD protection diode must be minimized. However, the parasitic capacitance of protection device can be reduced in a limited range. It is difficult for a device to have sufficient ESD protection level and small parasitic capacitance at the same time. Therefore, this thesis proposes a structure of low-loss I/O pad that can effectively reduce the effect of ESD protection diode at high frequency. The signal loss at K/Ka-bands is minimized by the principle of LC resonance. The low-loss I/O pad with dual-diode ESD protection has been implemented in 0.18μm CMOS process. It is confirmed from the high-frequency measurement that the signal losses of proposed structures are 6~10 times lower than the traditional structure. Finally, it is verified by various ESD tests that the proposed structure has sufficiently high capability of ESD protection.
Since the diodes is a single-conducting device, it is only suitable for providing an ESD path. The circuit requires an additional power-rail ESD clamp to provide complete protection. However, the ESD current usually requires a long distance to discharge through a power-rail ESD clamp. Therefore, this thesis proposes a structure of bi-directional P-type diode, which is controlled by the depletion region of the PN-junction. When the ESD events occur, the depletion region of channel will disappear and discharge the ESD current. In the normal operation, the depletion region should close the channel and have a sufficiently low leakage current. For the high-voltage applications, the lateral double-diffused MOS (LDMOS) is often used as the ESD protection device. However, the structure of LDMOS is complex and difficult to design. The ESD protection design is challenged in high-voltage operation. The structure of diode is simple and it has sufficient ESD protection level. Therefore, this thesis aims to improve the structure of diode. The P-type depletion diodes have been fabricated in 0.50μm CMOS process. It is confirmed from the DC measurement that the P-type depletion diodes have a sufficiently low leakage current under the normal operation. From the ESD tests, the idea of discharging ESD current through the channel is feasible but there is still room for improvement. Some improved structures and ideas will be mentioned in the future work of the final chapter.
摘   要 I
Abstract III
List of Tables VIII
List of Figures X

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Background of ESD 2
1.3 Test Standards of ESD 2
1.3.1 The Human Body Model (HBM) 3
1.3.2 The Machine Model (MM) 4
1.3.3 The Charged Device Model (CDM) 5
1.3.4 The Human Metal Model (HMM) 6
1.3.5 Electrostatic Discharge Sensitive (ESDS) 7
1.4 Basic ESD Protection Design for I/O Pad 8
1.4.1 ESD-Protection Design Window 9
1.4.2 The Considerations of High-Frequency Application 10
1.4.3 The Considerations of High-Voltage Application 11
1.5 Organization of This Thesis 12

Chapter 2 Introduction of ESD Protection Devices 13
2.1 Diode 13
2.2 Stacked Diodes 16
2.3 ESD Protection Diode with Local I/O Clamp 19
2.4 Whole-Chip ESD Protection Circuit Design 20
2.5 I/O Cell Library 21
2.6 Summary of This Chapter 23

Chapter 3 Low-Loss I/O Pad with ESD Protection for High-Frequency Circuits 24
3.1 Layout Design of Dual-Diode ESD Protection 24
3.2 Traditional I/O Pad with Dual-Diode ESD Protection 28
3.3 Low-Loss I/O Pad with Dual-Diode ESD Protection 31
3.4 Structure Design of Low-Loss I/O Pad 35
3.5 Simulation Methods and Results 47
3.6 Measurement Methods and Results 54
3.6.1 Two-Port S-Parameters Measurement 55
3.6.2 Ono-Port S-Parameter Measurement 60
3.6.3 TLP Measurement 67
3.6.4 VF-TLP Measurement 75
3.6.5 ESD Robustness 78
3.6.5 Failure Analysis 82
3.7 Comparison of Traditional and Proposed Structures 83
3.8 Comparison of Literature 85
3.9 Discussion of This Chapter 90
3.10 Summary of This Chapter 91

Chapter 4 Depletion Diodes for High-Voltage Applications 92
4.1 Traditional P-type Diode 92
4.2 P-type Depletion Diodes 94
4.3 Measurement Methods and Results 102
4.3.1 DC Measurement 103
4.3.2 Heating Test 110
4.3.3 TLP Measurement 112
4.3.4 ESD Robustness 121
4.4.4 Failure Analysis 123
4.4 Comparison of Traditional and Proposed Structures 124
4.5 Comparison of Literature 127
4.6 Discussion of This Chapter 129
4.7 Summary of This Chapter 131

Chapter 5 Conclusions and Future Works 132
5.1 Conclusions 132
5.2 Future Works 133

Reference 139
Vita 144
Publish List 145
[1] J. Vinson and J. Liou,“Electrostatic discharge in semiconductor devices: Protection techniques,” in Proc. IEEE Int. Conf. in Micro-electronics, vol. 88, no. 12, pp. 1878-1902, Dec. 2000.
[2] ESD association standard test method for electrostatic discharge sensitivity testing—human body model (HBM) component level, ANSI/ESD STM5.1-2007, 2007.
[3] M. Kelly, G. Servais, T. Diep, D. Lin, S. Twerefour, and G. Shah,“A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices,” in Proc. EOS/ESD Symp., 1995, pp. 175-185.
[4] K. Verhaege, G. Groeseneken, H. Maes, P. Egger, and H. Gieser,“Influence of tester, test method, and device type on CDM ESD testing,”in Proc. EOS/ESD-Symp., 1994, pp. 49-62.
[5] K. Muhonen, N. Peachey, and A. Testin, “Human metal model (HMM) testing challenges to using ESD guns” in Proc. EOS/ESD Symp., 2009, pp. 1-9.
[6] ESD association standard test method for electrostatic discharge sensitivity testing—machine model (MM) component level, STM5.3.1-2009, 2009.
[7] ESD association standard test method for electrostatic discharge sensitivity testing—human body model (HBM) component level, STM5.1-2007, 2007.
[8] ESD association standard test method for electrostatic discharge sensitivity testing—charged device model (CDM) component level, STM5.3.1-2009, 2009.
[9] M.-D. Ker and C.-Y. Lin “ESD protection consideration in nanoscale CMOS technology”in Proc. IEEE Int. Conf. on Nanotechnology, 2011, pp. 720-723.
[10] F. Roger, W. Reinprecht, and R. Minixhofer,“Process variation aware ESD design window considerations on a 0.18 μm analog, mixed-signal high voltage technology,” in Proc. EOS/ESD Symp., 2011, pp. 1-7.
[11] S. Sharma, E. Lagunas, S. Maleki, S. Chatzinotas, J. Grotz, J. Krause, and B. Ottersten, “Resource allocation for cognitive satellite communications in Ka-band (17.7–19.7GHz),” in Proc. IEEE Int. Conf. Communication Workshop, 2015, pp. 1646-1651.
[12] M. Nishikawa, K. Nakamura, H. Minda, K. Nakagawa, H. Hanado, S. Kawamura, S. Sugitani, and S. Shimizu, “Precipitation measurement using a dual Ka-band radar system for GPM/DPR algorithm development,” in Proc. IEEE Int. Geoscience and Remote Sensing Symp., 2012, pp. 1928-1931.
[13] R. Glogowski, J. Zurcher, C. Peixeiro, and J. Mosig, “A low-loss planar Ka-band antenna subarray for space applications,” IEEE Trans. Antennas Propag., vol. 61, no. 9, pp. 4549-4557, Sep. 2013.
[14] S. Cao, J. Chun, S. Beebe, and R. Dutton, “ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2301-2311, Sep. 2010.
[15] K. Gong, H. Feng, R. Zhan, and A. Wang, “A study of parasitic effects of ESD protection on RF ICs” IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp. 393-402, Jan. 2002.
[16] M.-D. Ker, C.-Y. Lin, and Y.-W. Hsiao, “Overview on ESD protection designs of low parasitic capacitance for RF ICs in CMOS technologies,” IEEE Trans. Device Mater. Reliab., vol. 11, no. 2, pp. 207-218, Jun. 2011.
[17] M.-D. Ker and Y.-W. Hsiao, “ESD protection design with low capacitance consideration for high-speed/high-frequency I/O interfaces in integrated circuits,”Recent Patents on Engineering, vol. 1, no. 2, pp. 131-145, Jun. 2007.
[18] M. Mergens, M. Mayerhofer, J. Willemen, and M. Stecher, “ESD protection considerations in advanced high-voltage technologies for automotive,” in Proc. EOS/ESD, 2006, pp. 54-63.
[19] J.-S. Kim and W.-H. Lee “Offset-compensated operational amplifier for gray voltage generation of 262144 color QVGA LCD driver IC,” in Proc. IEEE Asian Solid-State Circuits Conf., pp. 368-371, Nov. 2007.
[20] Y.-C. Huang, C.-T. Dai, and M.-D. Ker, “Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process,”in Proc. IEEE Int. Symp. on Next-Generation Electronics, 2013, pp.116-119.
[21] F. Ma, B. Zhang, Y. Han, J. Zheng, B. Song, S. Dong, and H. Liang, “High holding voltage SCR-LDMOS stacking structure with ring-resistance- triggered technique,” IEEE Electron Device Letters, vol. 34, no. 9, pp.1178-1180, 2013.
[22] V. DeHeyn, G. Groesenken, B. Keppens, M. Natarajan, L. Vacaresse, and G. Gallopyn, “Design and analysis of new protection structures for Smart Power Technology with controlled trigger and holding voltage,” in Proc. Int. Reliab. Physics Symp., 2001, pp. 253-258.
[23] Y. Li, J. Liou, J. Vinson, and L. Zhang, “Investigation of LOCOS- and polysilicon-bound diodes for robust electrostatic discharge (ESD) applications,” IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 814-819, Apr. 2010.
[24] C.-Y. Lin, M.-L. Fan, M.-D. Ker, L.-W. Chu, J.-C. Tseng, and M.-H. Song“Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS,” in Proc. Int. Reliab. Physics Symp., Jun. 2014, pp. EL.1.1-EL.1.4.
[25] M.-D. Ker and C.-Y. Chang, “ESD protection design for CMOS RF integrated circuits using polysilicon diodes,” Microelectron. Reliab., vol. 42, no. 6, pp. 863- 872, Jun. 2002.
[26] S. Thijs, M. Okushima, J. Borremans, P. Jansen, D. Linten, M. Scholz, P. Wambacq, and G. Groeseneken, “Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications,”in Proc. IEEE Custom Integrated Circuits Conf., pp. 49-52, 2008.
[27] C.-Y Chang and M.-D. Ker, “On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process,” in Proc. IEEE Int. Symp. on VLSI Tech., Syst., and Applications, pp. 240-243, 2001.
[28] M.-D. Ker and T.-Y. Chen,“Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes,” in Proc. IEEE Int. Symp. on Circuits and Syst., 2001, pp. 758-761.
[29] S. Maeda, M. Tanaka , Y. Otsuk, M. Tsukuda , and Y. Morishita, “Area-efficient ESD design using power clamps distributed outside I/O cell ring,” in Proc. EOS/ESD Symp, 2016.
[30] Y. Koo, K. Lee, J. Kwack, J. Won, and K. Kim, “The design of Bi-CMOS LVDS output buffer with ESD protection circuit using 90nm CMOS technology,” in Proc. Int. Conf. on Advances in Electronics and Micro-elevtronics, Oct. 2008, pp. 54-58.
[31] S. Aloui, E. Kerherve, J. Begueret, R. Plana, and D. Belot, “Optimized pad design for millimeter-wave applications with a 65 nm CMOS RF technology,” in Proc. Eur. Microw. Conf., Sep. 2009, pp. 1187-1190.
[32] A. Dong, J. Salcedo, S. Parthasarathy, Y. Zhou, S. Luo, J. Hajjar, and J. Liou, “ESD protection structure with reduced capacitance and overshoot voltage for high speed interface application,” Microelectronics Reliab., vol. 79, pp. 201-205, Mar. 2017.
[33] J.-T. Chen and M.-D. Ker,“On-chip ESD protection devices for high-speed I/O applications in CMOS technology,” IEEE Trans. Electron Devices, vol. 64, no. 10, pp. 3979-3985, Oct. 2017.
[34] L. Zhu and K. Wu, “Accurate circuit model of interdigital capacitor and its application to design of new quasi-lumped miniaturized filters with suppression of harmonic resonance,” IEEE Trans. Microwave Theory Tech., vol. 48, pp. 347-356, Mar. 2000.
[35] J.-C. Tseng, C.-T. Hsu, C.-K. Tsai, Y.-C. Liao, and M.-D. Ker, “ESD protection design for low trigger voltage and high latch-up immunity,” in Proc. IEEE Int. Physical and Failure Analysis of Integrated Circuits Symp., 2010, pp. 32-35.
[36] P. Renaud, A. Gendron, M. Bafleur, and N. Nolhier, “High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology,” in Proc. IEEE Bipolar/BiCMOS Circuits Tech. Meeting, 2007, pp. 226-229.
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