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研究生:周民淳
研究生(外文):Chou, Min-Chun
論文名稱:具輸出阻抗設計之電壓平方固定導通時間控制降壓轉換器
論文名稱(外文):A V2-Type Constant On-Time Control Buck Converter with Output Impedance Design
指導教授:葉美玲葉美玲引用關係
指導教授(外文):Yeh, Mei-Ling
口試委員:林嘉洤黃淑絹葉美玲
口試委員(外文):Lin, Jia-ChuanHuang, Shu-ChuanYeh, Mei-Ling
口試日期:2019-01-18
學位類別:碩士
校院名稱:國立臺灣海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:84
中文關鍵詞:固定輸出阻抗適應性電壓位置技術電壓平方迴路固定導通時間控制
外文關鍵詞:Constant output impedanceadaptive voltage position techniqueV2 loopconstant on-time control
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隨著科技發展,為了提升電力能源的轉換效率,電源轉換器的設計顯得格外的重要。由於近幾年來為了減少面積成本,電源管理積體電路也被廣泛的應用。除此之外,處理器持續降低工作電壓以及提升操作電流的需求,當操作電流瞬間變動時,容易使工作電壓產生較大突波,導致應用於處理器的降壓轉換器面臨較嚴苛的挑戰。常見解決辦法則是透過輸出阻抗設計,實現適應性電壓位置技術。另外一般電子產品長時間應用於輕載,為了改善輕載效率,可以透過固定導通時間控制,使產品可以於輕載時自動降頻以改善開關切換損耗。
本研究實現一具有輸出阻抗設計之降壓轉換器晶片,控制架構採用增強型電壓平方迴路固定導通時間控制。晶片製程使用TSMC 0.35um Mixed-Signal 2P4M Polycide 5V製程實現,輸入電壓範圍在3.3V至4.2V,輸出電壓為1.2V,切換頻率在1.2MHz,負載電流範圍為25mA至600mA,轉換效率最高可達91.1%。使用電感值3.3uH,電容值16uF。
Along with the development of technology, in order to improve the efficiency of power and energy, the design of power converter is particularly important. In recent years, power management integrated circuits have also been widely used to reduce the area cost. Besides, the processor continues to reduce the operating voltage and increase the operating current. When the operating current changes instantaneously, it is easy to cause a large surge of the operating voltage, which causes the buck converter applied to the processor to face more severe challenges. A common solution is to implement adaptive voltage position techniques through output impedance design. In addition, general electronic products are used for light loads for a long time. In order to improve light load efficiency, the constant on-time control can be used to enable the product to automatically reduce frequency at light loads to improve switching loss.
In this study, a buck converter chip with an output impedance design is implemented. The control architecture uses the constant on-time (COT) control with the enhanced V2 loop. The chip is implemented using the TSMC 0.35um Mixed-Signal 2P4M Polycide 5V process with an input voltage range of 3.3V to 4.2V, an output voltage of 1.2V, a switching frequency of 1.2MHz, a load current range of 25mA to 600mA, and a conversion efficiency of up to 91.1%. The inductance value is 3.3uH and the capacitance value is 16uF.

Keywords: Constant output impedance, adaptive voltage position technique, V2 loop, constant on-time control.
摘要 I
Abstract II
目錄 III
圖目錄 VI
表目錄 IX
第一章 緒論 1
1.1 研究動機與目標 1
1.2 論文架構 3
第二章 切換式電源轉換器暨控制概論 4
2.1切換式降壓轉換器介紹 6
2.1.1 同步整流與非同步整流介紹 6
2.1.2 功率級工作原理 8
2.2 傳統定頻控制架構 11
2.2.1 電壓模式控制架構 12
2.2.2 電流模式控制架構 14
2.3 常見漣波控制基本架構 16
2.3.1 遲滯控制 17
2.3.2 固定導通時間控制 19
2.3.3 固定截止時間控制 21
2.3.4 電壓平方控制 23
2.4 控制架構比較與結論 23
第三章 固定導通時間控制模型及輸出阻抗設計介紹 25
3.1 固定導通時間控制模型 25
3.1.1 回顧傳統平均模型 25
3.1.2 電流模式固定導通時間控制之描述函數 28
3.1.3 電壓平方固定導通時間控制之描述函數 31
3.1.4 增強型電壓平方模式固定導通時間控制之描述函數 32
3.2 適應性電壓位置技術 36
3.2.1 恆定輸出阻抗設計概念 36
3.2.2 實現AVP功能之CMCOT控制架構 38
第四章 具輸出阻抗設計之增強型V2COT控制降壓轉換器實現與電路設計 42
4.1 電路架構實現 42
4.1.1 DCR電流感測電路 44
4.1.2 AVP實現之輸出阻抗設計 45
4.2 子電路設計與模擬 47
4.2.1 偏壓電路(Bias circuit) 47
4.2.2 二級放大器(Two-stage OPA) 49
4.2.3 能隙參考電壓電路 (Bandgap reference voltage circuit) 50
4.2.4 比較器 (Comparator) 53
4.2.5 固定導通時間產生器 (Constant on-time generator) 55
4.2.6 最小關閉時間產生器 ( Min off-time generator) 57
4.2.7 零電流偵測電路 ( Zero current detection circuit) 59
4.2.8 軟啟動電路 ( Soft start circuit) 61
4.2.9 非重疊導通電路 ( Non-overlapping Circuit) 62
第五章 電路佈局與模擬結果 65
5.1 晶片設計流程 65
5.2 晶片佈局規劃及考量 66
5.3 晶片後模擬結果 68
5.3.1 頻率變化 68
5.3.2 暫態響應 (Transient response) 68
5.3.3 輸出電壓漣波 (Output Voltage Ripple) 70
5.3.4 效率模擬規格 73
5.4 本研究晶片設計規格 74
5.5 相關參考文獻比較表 75
第六章 結論與未來展望 77
6.1 結論 77
6.2 未來展望 77
參考文獻 79
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