臺灣博碩士論文加值系統

自動測試機台(ATE)用於測試積體電路(Integrated Circuit, IC)，測試其功能與性能並將有缺陷IC排除。接收器(Receiver)是自動測試機台裡重要的核心模組，其將使用者定義的符號資料(Symbol Data)、探測時序(Strobe Timing)、理想響應(Golden Response)等資訊組合，以接收待測電路響應(DUT Response)。
本篇論文提出基於邊緣產生器池(Edge Generator Pool)接收器架構，實現在Xilinx Spartan-6 FPGA，使用特殊設計可程式化延遲線作為時序電路，可精準的控制接收位置的時間，並透過校準機制提升接收位置的準確度。設計規格具有100 Msps(Mega Symbol Per Second)的符號產生頻率，每個符號為單個探測點(Single Strobe)，並具備200 ps的解析度及其誤差小於90 ps的精確度。

The automatic test equipment (ATE) is used to test integrated circuit (IC). It can not only test its functionality and performance, but also prevent defective ICs from entering the market. The receiver is a very important module in ATE. It is responsible for parsing user-defined symbol data, including strobe timing and golden response, to capture the device under test (DUT) response.
This paper proposes an edge generator pool (EG-Pool) based receiver architecture implemented on Xilinx Spartan-6 FPGA. The proposed receiver uses EG-Pool with programmable delay line to place the strobes with high timing resolution. After calibration, we can enhance the strobe placement accuracy.
The proposed FPGA receiver achieves 100 Msps, single strobe point for each symbol with 200 ps resolution and accuracy higher than 90 ps.

口試委員會審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
目錄 v
圖目錄 vii
表目錄 ix
第1章 緒論 1
1.1 研究動機與目的 1
1.2 相關研究 2
1.3 研究貢獻 3
1.4 論文架構 3
第2章 接收器介紹與先前研究 4
2.1 自動測試機台(Automatic Test Equipment, ATE) 4
2.2 接收器(Receiver)與來回傳遞延遲(Round Trip Delay) 5
2.3 先前研究 7
2.3.1 格式器架構(Formatter Architecture) 7
2.3.2 邊緣產生器池控制器(EG-Pool Controller) 8
2.3.3 邊緣產生器池(Edge Generator Pool) 11
2.3.4 邊緣產生器(Edge Generator) 12
2.3.5 邊緣組合器(Edge Combiner) 13
2.3.6 可程式化延遲線(Programmable Delay Line) 13
2.3.7 可程式化延遲線之校準(Calibration) 15
第3章 以FPGA實現接收器架構 16
3.1 符號(Symbol)資料定義與說明 17
3.2 校正來回傳遞延遲(Calibrate Round Trip Delay) 18
3.3 接收器架構 19
3.3.1 對齊器(Aligner) 19
3.3.2 探測脈衝產生器(Strobe Generator) 19
3.3.3 校正來回傳遞細延遲之問題 21
3.3.4 校正來回傳遞細延遲之方法 23
3.3.5 捕捉器(Capturer) 26
第4章 接收器之實作 27
4.1 實驗環境設置 27
4.2 探測脈衝產生器之實作 28
4.3 量測來回傳遞延遲實驗設置 33
第5章 實驗結果 34
5.1 探測脈衝產生器功能驗證 34
5.2 探測脈衝產生器線性度分析 36
5.3 量測週期性訊號 41
5.4 來回傳遞延遲量測結果 42
5.5 探測脈衝擺置精確度(Strobe Placement Accuracy) 42
5.6 FPGA資源使用與功率消耗 43
第6章 結論與未來研究方向 44
6.1 結論 44
6.2 未來研究方向 44
參考文獻 45

[1]Quad Pin Timing Formatter ADATE207, Analog Device Inc, 2007.
[2]K.-T. Li, “Design and Implementation of 25-ps Resolution, EG-Pool Based Formatter on FPGA,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2016.
[3]Jaeseok Park, et al. ”Integration of Dual Channel Timing Formatter System for High Speed Memory Test Equipment,” in International SoC Design Conference, 2012, pp. 185 – 187.
[4]A. R. Syed, “RIC/DICMOS - Multi-channel CMOS Formatter,” in International Test Conference, 2003, pp. 175 – 184.
[5]Luca Mostardini, et al. “FPGA-based Low-cost Automatic Test Equipment for Digital Integrated Circuits,” in International Workshop on Intelligent Data Acquisition and Advanced Computing System: Technology and Applications, 2009, pp. 32 – 37.
[6]Y.-Y. Chen, “An FPGA-based Sub-nanosecond Low-cost Timing Generator and Formatter,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2013.
[7]P.-C. Shu, “A High Resolution and High Accuracy FPGA Formatter Prototype,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2014.
[8]C.-L. Hsiao, “A High-Resolution FPGA Formatter with Symbol-Stretching and Inversion Capability,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2016.
[9]The Fundamentals of Digital Semiconductor Testing, Soft Test, 2013.
[10]Y.-K. Huang, “An FPGA-based Temperature Compensated 200-ps Resolution Multi-channel Formatter,” M.S. thesis, National Taiwan University, Taipei, Tai-wan, 2017.
[11]C.-A. Lee, “Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2015.
[12]G.-H. Hou, “An FPGA-based 200-ps Resolution 16-channel Formatter with Low Resource Usage,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2018.
[13]Constrains Guide, Xilinx, 2012.
[14]Spartan-6 FPGA Configurable Logic Block, Xilinx, 2010.