臺灣博碩士論文加值系統

自從三星在2015年量產20nm DRAM產品後，DRAM的發展進入1X,1Y,1Z的時代，為了滿足微縮後的需求，如何在有限的面積裡維持足夠大的電容值防止讀取錯誤為DRAM微縮之主要問題，改變電容有效接觸面積或介電常數為主要解決方法，可用改變電容結構或改變材料來解決，然而高介電常數之材料勢必有較高漏電流，必須在滿足低漏電流情況下，尋求最高電容值之電容。另一方面近來，Spin-Transfer Torque Magnetic Radom Access Memory (STT-MRAM)已經成為下世代重要的非揮發性記憶體的，STT-MRAM是利用電流經Magnetic Tunneling Junction (MTJ)後形成自旋極化電流，能翻轉鐵磁薄膜中的電子磁矩造成電阻值改變作為存取資料的訊號，STT-MRAM有許多優點：非揮發特性、讀寫速度快、低能耗、高讀寫次數上限。
本論文第一部分研究以二氧化鋯為主之介電層作為DRAM電容，在原子層沉積過程中，在二氧化鋯介電層中成長一層氧化鋁形成二氧化鋯/氧化鋁/二氧化鋯薄膜，探討成長氧化鋁於二氧化鋯之位置對其介電層之電特性之影響，另外探討原子層沉積溫度變化對電特性之影響與氧化層可靠度分析，預測氧化層在DRAM正常操作下，電容壽命是否可達十年。另一部分，使用TCAD模擬分析氧化鋁在二氧化鋯中不同位置對漏電流之影響，並解釋不同位置的氧化鋁對非對稱電流之關係。
本論文第二部分以Landau-Lifshitz-Gilbert(LLG)公式為基礎，模擬電流流經垂直式MTJ(pMTJ)時，垂直式MTJ之磁矩隨時間變化導致高電阻阻態(HRS)與低電電阻阻態(LRS)的變化，此模型的準確性已與理論值進行驗證。另一方面利用其他文獻實驗參數進行模擬，依據Fokker-Planck理論，因熱擾動造成磁矩之初始角產生機率分布，使用Monte Carlo方法分析STT-MRAM之Write Error Rate(WER)可靠度分析，探討其參數對其影響並畫出Shmoo Plot分析在特定電流和時間內能夠達到WER標準值1E-6，並考慮製程所致垂直式MTJ之直徑與厚度誤差對可靠度之影響。

Since Samsung released 20nm DRAM products in 2015, DRAM has now migrated to the 1x, 1y, 1z era. The main challenge is how to maintain the sufficient capacitance in the limited area to prevent the sensing error as DRAM capacitor scaling. How to increasing the effective area of capacitor or decrease the equivalent oxide thickness (EOT) is the main solution. The problem could be solved by means of changing the structure or materials. However, high dielectric constant oxide generally has the lower energy gap. Therefore, under the condition of the low leakage current, achieve the minimum of equivalent oxide thickness (EOT) to be the next generation DRAM products. On the other hand, Spin-Transfer Torque Magnetic Radom Access Memory (STT-MRAM) has emerged as a promising candidate for the next generation of non-volatile memory. STT-MRAM switching the magnetization through Magnetic Tunneling Junction (MTJ) with polarized current to change their resistance state as data. STT-MRAM has many advantages, including non-volatility, high speed, low power dissipation, and high endurance.
In the first part, investigate on ZrO2-based film as DRAM capacitor. During atomic layer deposition (ALD) process, fabricate ZrO2-Al2O3-ZrO2 (ZAZ) film and investigate on the relationship between the locations of interposed layer Al2O3 and electrical characteristics. On the other hand, analyze the ZAZ film with the various location at the different ALD process temperature, and conduct time dependent dielectric breakdown (TDDB) analysis to prevent whether the dielectric has 10-year lifetime on the normal operation or not. In the next chapter, simulate the leakage current of ZAZ film with the various location of Al2O3 the by TCAD simulation, and explain the asymmetry factor of leakage current with the various location of Al2O3
In the second part, establish the model of perpendicular Magnetic Tunneling Junction (pMTJ) on the basis of Landau-Lifshitz-Gilbert (LLG) equation. Through the drive current, the dynamic magnetization as a function of time would be switched between high resistant state (HRS) and low resistant state (LRS). The accuracy of the model had been verified with the theorems. Furthermore, according to Fokker-Planck theorem, simulate the initial angle distribution of magnetization owing to thermal fluctuation. Based on the other’s experiment, run the LLG-based model many times to predict write error rate (WER) of STT-MRAM by means of Monte Carlo method and plot Shmoo plot to determine the operation point for WER=1E-6. On the other hand, analyze the change of reliability issue plot after considering the diameter and thickness variation of MTJ owing to process variation.

口試委員會審定書 #
致謝 4
Related Publications: (相關論文發表) i
中文摘要 ii
ABSTRACT iii
CONTENTS v
LIST OF FIGURES vii
LIST OF TABLES x
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Thesis Organization 3
1.3 Reference 5
Chapter 2 Fabrication and Characterization of DRAM MIM Capacitor 7
2.1 Introduction 7
2.2 Process Flow of DRAM Capacitor 11
2.3 Electrical Characterization 12
2.4 ALD Process Fabrication 15
2.5 TDDB Analysis 18
2.6 Summary 20
2.7 Reference 21
Chapter 3 Conduction Mechanism of DRAM MIM Capacitor 24
3.1 Introduction 24
3.2 The Leakage Suppression by Interposed Layer Al2O3 27
3.3 Asymmetric Current Analysis 29
3.4 Conduction mechanism of MIM Capacitor 36
3.5 Summary 39
3.6 Reference 40
Chapter 4 Conduction Mechanism of DRAM MIM Capacitor 42
4.1 Introduction 42
4.2 STT-MRAM macro-model development 45
4.3 Electrical Characteristics in STT-MRAM 51
4.4 Statistical Switching in STT-MRAM 56
4.5 WER Analysis for Write Operation 59
4.6 Summary 65
4.7 Reference 66
Chapter 5 Summary and Future Work 69
5.1 Summary 69
5.2 Future Work 70

1.1Joseph Izraelevitz, Jian Yang, Lu Zhang, Juno Kim, Xiao Liu, Amirsaman Memaripour, Yun Joon Soh, Zixuan Wang, Yi Xu, Subramanya R. Dulloor, Jishen Zhao, Steven Swanson, “Basic Performance Measurements of the Intel Optane DC Persistent Memory Module,” arXiv, 2 Apr. 2019.
1.2P. J. Nair et. al., “architectural framework for assisting DRAM scaling by tolerating high error rates,” ACM SIGARCH Computer Architecture News , p. Volume 41 Issue 3, 3 Jun. 2013.
1.3J. M. Park et al., "20nm DRAM: A new beginning of another revolution," 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, 2015, pp. 26.5.1-26.5.4.
1.4S. Ikeda et al., "Magnetic Tunnel Junctions for Spintronic Memories and Beyond," in IEEE Transactions on Electron Devices, vol. 54, no. 5, pp. 991-1002, May 2007.
1.5Dongsoo Woo., “DRAM: Its Challenging History and Future”, IEEE International Electron Device Meeting, short course, 2018.
1.6S. Yu and P. Chen, "Emerging Memory Technologies: Recent Trends and Prospects," in IEEE Solid-State Circuits Magazine, vol. 8, no. 2, pp. 43-56, Spring 2016.
1.7W. Jeon, O. Salicio, A. Chaker, P. Gonon and C. Vallée, "Controlling the Current Conduction Asymmetry of HfO2 Metal–Insulator–Metal Diodes by Interposing Al2O3 Layer," in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 402-406, Jan. 2019.
1.8G. Hu et al., "Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 38.3.1-38.3.4.
1.9R. Dorrance, F. Ren, Y. Toriyama, A. A. Hafez, C. K. Yang and D. Markovic, "Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs," IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 878-887, Apr., 2012.
2.1Dongsoo Woo., “DRAM: Its Challenging History and Future”, IEEE International electron Device Meeting, short course, 2018.
2.2Milan Pešić et al “Low leakage ZrO2 based capacitors for sub 20 nm dynamic random access memory technology nodes”, Journal of Applied Physics 119, 064101, Feb, 2016.
2.3Ming-Yen Li , Bin-Siang Tsai, Pei-Chuen Jiang, Hsiao-Che Wu, Yung-Hsien Wu, Yu-Jen Lin, “Structure and property changes of ZrO2/Al2O3/ZrO2 laminate induced by low temperature NH3 annealing applicable to metal-insulator-metal capacitor”, Thin Solid Films, Vol. 518, issue 18, 1, Jul. 2010.
2.4Y. Hwamg et al., “An Overview and Future Challenges of High Density DRAM for 20nm and Beyond”
2.5Kinam Kim, "Technology for sub-50nm DRAM and NAND flash manufacturing," IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. pp. 323-326 Washington, DC, 2005.
2.6J. Lee et al., "New Method for Reduction of the Capacitor Leakage Failure Rate Without Changing the Capacitor Structure or Materials in DRAM Mass Production," in IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 4839-4845, Nov., 2018.
2.7W. Jeon, Y. Kim, C. H. An, C. S. Hwang, P. Gonon and C. Vallée, "Demonstrating the Ultrathin Metal–Insulator– Metal Diode Using TiN/ZrO2–Al2O¬¬3–ZrO2 Stack by Employing RuO2 Top Electrode," in IEEE Transactions on Electron Devices, vol. 65, no. 2, pp. 660-666, Feb., 2018
2.8W. Jeon, O. Salicio, A. Chaker, P. Gonon and C. Vallée, "Controlling the Current Conduction Asymmetry of HfO2 Metal–Insulator–Metal Diodes by Interposing Al2O3 Layer," in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 402-406, Jan. 2019.
2.9S. Knebel, U. Schroeder, D. Zhou, T. Mikolajick and G. Krautheim, "Conduction Mechanisms and Breakdown Characteristics of Al2O3-Doped ZrO2 High-k Dielectrics for Three-Dimensional Stacked Metal–Insulator–Metal Capacitors," in IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, pp. 154-160, Mar. 2014.
2.10P. Gonon, and C. Vallee, “Modeling of nonlinearities in the capacitance-voltage characteristics of high-k metal-insulator-metal capacitors”, Appl. Phys. Lett. 90, 142906, Apr, 2007.
2.11Wenke Weinreich, Ahmed Shariq, Konrad Seidel, and Jonas Sundqvist, “Detailed leakage current analysis of metal–insulator–metal capacitors with ZrO2, ZrO2/ SiO2/ZrO2, and ZrO2/Al2O3/ZrO2 as dielectric and TiN electrodes”, Journal of Vacuum Science & Technology B 31, 01A109, Dec, 2012.
2.12J. W. McPherson, Jinyoung Kim, A. Shanware, H. Mogul and J. Rodriguez, "Trends in the ultimate breakdown strength of high dielectric-constant materials," in IEEE Transactions on Electron Devices, vol. 50, no. 8, pp. 1771-1778, Aug. 2003.
2.13Joo-Hyung Kim, Velislava Ignatova, Peter Kücher, Johannes Heitmann, Lars Oberbeck, Uwe Schröder, ” Physical and electrical characterization of high-k ZrO2 metal–insulator–metal capacitor ”, Thin Solid Films, Vol. 516, Issue 23, 1, Oct., 2008.
2.14Christopher L. Henderson, “Semiconductor Reliability and Product Qualification”, IRPS, IEEE International Reliability Physics Symposium (IRPS), short course, Mar., 2018.
3.1O. Fursenko, J. Bauer, G. Lupina, P. Dudek, M. Lukosius, Ch. Wenger, P. Zaumseil, “Optical properties and band gap characterization of high dielectric constant oxides”, Thin Solid Films Volume 520, Issue 14, Pages 4532-4535, 1, May, 2012.
3.2Milan Pesic, Steve Knebel , Kyuho Cho , Changhwa Jung, Jaewan Chang, Hanjin Lim, Nadiia Kolomiiets, Valeri V.Afanas’ev, Thomas Mikolajick, UweSchroeder, “Conduction barrier offset engineering for DRAM capacitor scaling”, Solid-State Electronics, Volume 115, Part B, Pages 133-139, Jan., 2016.
3.3Wenke Weinreich, Ahmed Shariq, Konrad Seidel, and Jonas Sundqvist, “Detailed leakage current analysis of metal–insulator–metal capacitors with ZrO2, ZrO2/SiO2/ZrO2, and ZrO2/Al2O3/ZrO2 as dielectric and TiN electrodes”, Journal of Vacuum Science & Technology B 31, 01A109, Feb., 2013.
3.4Sang Yeon Lee, Jaewan Chang, Jaehyung Choi, Younsoo Kim, HanJin Lim, Hyeongtag Jeon, Hyungtak Seo, “Investigation of ultrathin Pt/ZrO2-Al2O3- ZrO2/TiN DRAM capacitors Schottky barrier height by internal photoemission spectroscopy”, Current Applied Physics, 17, 267-271, Dec., 2017.
3.5Balazs Kralik, Eric K. Chang, and Steven G. Louie, “Structural properties and quasiparticle band structure of zirconia”, PHYSICAL REVIEW B VOLUME 57, NUMBER 12, Mar., 1998.
3.6Woojin Jeon,z Hoi-Sung Chung, Daekwon Joo, and Sang-Won Kang, “TiO2/Al2O3/TiO¬2¬ Nanolaminated Thin Films for DRAM Capacitor Deposited by Plasma-Enhanced Atomic Layer Deposition” Electrochemical and Solid-State Letters, H19-H21, Nov.,2007.
3.7Shi-Jin Ding, Jun Xu, Yue Huang, Qing-Qing Sun, David Wei Zhang, and Ming-Fu Li, “Electrical characteristics and conduction mechanisms of metal-insulator-metal capacitors with nanolaminated dielectrics” Appl. Phys. Lett. 93, 092909, Jul., 2008.
3.8W. Jeon, O. Salicio, A. Chaker, P. Gonon and C. Vallée, "Controlling the Current Conduction Asymmetry of HfO2 Metal–Insulator–Metal Diodes by Interposing Al2O3 Layer," IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 402-406, Jan. 2019.
4.1G. Hu et al., "Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 38.3.1-38.3.4.
4.2J. Kim, A. Chen, B. Behin-Aein, S. Kumar, J. Wang and C. H. Kim, "A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies," 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015, pp. 1-4.
4.3A V Khvalkovskiy, D Apalkov, S Watts, R Chepulskii, R S Beach, A Ong, X Tang, A Driskill-Smith, W H Butler, P B Visscher, “Basic principles of STT-MRAM cell operation in memory arrays”, Journal of Physics D: Applied Physic, 31, Jan., 2013.
4.4M. Sato, and Y. lshii, “Simple and approximate expressions of demagnetizing factors of uniformly magnetized rectangular rod and cylinder”, Journal of Applied Physics 66, 983, 31, Mar., 1989.
4.5Bernard Dieny, Ronald B. Goldfarb, Kyung-Jin Lee, “Introduction to Magnetic Random-Access Memory”, First Edition, 2017.
4.6C. J. Lin et al., "45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell," 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, 2009, pp. 1-4.
4.7K. Lee and S. H. Kang, "Design Consideration of Magnetic Tunnel Junctions for Reliable High-Temperature Operation of STT-MRAM," in IEEE Transactions on Magnetics, vol. 46, no. 6, pp. 1537-1540, Jun., 2010.
4.8M. Madec, J. Kammerer and L. Hébrard, "Compact Modeling of a Magnetic Tunnel Junction—Part II: Tunneling Current Model," in IEEE Transactions on Electron Devices, vol. 57, no. 6, pp. 1416-1424, Jun., 2010
4.9M. Julliere, “Tunneling between ferromagnetic films”, Physics Letters A, Volume 54, Issue 3, Pages 225-22, 8, Sep., 1975.
4.10J. C. Slonczewski, “Conductance and exchange coupling of two ferromagnets separated by a tunneling barrier”, Phys. Rev. B 39, 6995, 1, Apr, 1989.
4.11W. F. Brinkman, R. C. Dynes, and J. M. Rowell, “Tunneling Conductance of Asymmetrical Barriers”, Journal of Applied Physics, 41, 1970.
4.12C. J. Lin et al., "45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell," IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, pp. 1-4., 2009.
4.13K. Lee and S. H. Kang, "Design Consideration of Magnetic Tunnel Junctions for Reliable High-Temperature Operation of STT-MRAM," in IEEE Transactions on Magnetics, vol. 46, no. 6, pp. 1537-1540, Jun. 2010.
4.14V. Drewello, J. Schmalhorst, A. Thomas, and G. Reiss, “Evidence for strong magnon contribution to the TMR temperature dependence in MgO based tunnel junctions”, Phys. Rev. B 77, 014440, 31, Jan, 2008.
4.15K. Ikegami et al., "Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques," IEEE International Electron Devices Meeting, pp. 28.1.1-28.1.4., San Francisco, CA, 2014.
4.16C. Park et al., "Temperature Dependence of Critical Device Parameters in 1 Gb Perpendicular Magnetic Tunnel Junction Arrays for STT-MRAM," IEEE Transactions on Magnetics, vol. 53, no. 2, pp. 1-4, Feb., 2017.
4.17W. H. Butler et al., "Switching Distributions for Perpendicular Spin-Torque Devices Within the Macrospin Approximation," in IEEE Transactions on Magnetics, vol. 48, no. 12, pp. 4684-4700, Dec. 2012.
4.18Jung-Hwan Moon, Tae Young Lee & Chun-Yeol You, “Relation between switching time distribution and damping constant in magnetic nanostructure”, Scientific reports, 16, Aug., 2018.
4.19R. De Rose et al., "A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 3, pp. 1086-1095, Mar., 2018.
4.20N. Xu et al., "Rare-Failure Oriented STT-MRAM Technology Optimization," IEEE Symposium on VLSI Technology, pp. 187-188., Honolulu, HI, 2018.