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研究生:張景傑
研究生(外文):Ching-Chieh Chang
論文名稱:無線雷達收發機與有線發射機之設計
論文名稱(外文):Design of Wireless Radar Transceivers and Wireline Transmitter
指導教授:李致毅李致毅引用關係
口試委員:劉宗德彭朋瑞
口試日期:2019-06-28
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:英文
論文頁數:67
中文關鍵詞:雷達系統無線收發機有線發射機脈衝振幅調變
DOI:10.6342/NTU201901651
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在現代,資料傳輸系統被廣泛應用在我們的生活中,而隨著資料傳輸量需求提升,通訊系統也快速地演進,並在科技進步中扮演舉足輕重的角色。本論文基於無線傳輸與有線傳輸的需求,分別設計一無線收發機與一有線發射機。
(一) 無線收發機
無線收發機與有線資料收發機之最大差別於在於其頻寬之限制。無線傳輸為射頻之應用屬於窄頻帶操作,且針對不同應用,頻帶的選擇上必須依照ISM 頻帶規範,也因此收發機的設計上必須加以考量以符合使用上規範。本論文提出應用於24-GHz 頻帶內之車用雷達收發機。系統為一發四收之架構,且具備一頻率合成器用以提供系統所需時脈。發射端採用二級功率放大器,而整體接收端包含二級低雜訊放大器、威爾金森功率分配器、混波器、可變增益放大器以便取出中頻訊號得以透過後段之數位訊號處理單元分析特定目標之距離與相對速度資訊。此雷達系統之發射端在消耗120 mW 下能提供6 dBm 的輸出功率;單一接收端在消耗30 mW下能提供26 dB 的增益,頻率產生器功耗為120 mW 且能提供250 MHz 的FMCW調變範圍。此雷達系統在40 nm CMOS 製程實現之面積為3.3 mm2.
(二)有線發射機
為有效利用製程頻寬,有線資料傳輸基於傳統的NRZ 資料格式,發展出了脈衝振幅調變資料格式。本論文提出一奠基於脈衝振幅調變技術之PAM-8 有線發射機。設計包含高速類比前端電路用以驅動產生PAM-8 輸出訊號,並加入包含2 個抽頭的前饋等化器以補償通道損失。在測試方面,系統內建數位電路之偽亂數產生器(PRBS-7, PRBS-15, PRBS-23, PRBS-31),且資料序列可透過多工器產生高速資料。針對不同操作速率,電路皆針對其資料頻寬及功耗進行考量。另外為解決高速多工器因實體布局及製程變異所造成的資料取樣點偏移的問題,系統內建一時脈調節電路用以動態確保資料取樣位置。此系統支援 NRZ, PAM4, PAM8 三種資料型態之輸出,且能在451 mW 的功率消耗下能以單通道傳輸每秒高達八百億位元之資料量,此發射端晶片在40 nm CMOS 製程實現下面積為1.3 mm2.
In modern society, data transmission systems are widely employed in our life. With the increasing requirement for quantity of data transmission, communication systems evolve rapidly and act as an important role in the development of modern technology. Based on requirement for wireless and wireline communication, this Thesis presents the design of wireless transceivers and wireline transmitter.
(I) Wireless radar transceiver
The major difference between wireless and wireline data transmission is the limitation of bandwidth. Wireless transmission belonging to radio-frequency application is narrow band operation. Fitted with different applications, the choosing of the frequency band must obey the ISM band regulation. The design of transceivers should be taken care of to follow the regulation. This Thesis presents a set of transceivers to be applicable in 24-GHz automobile radar system. One transmitter and four receivers are employed in the system which also includes a frequency synthesizer to provide required internal clock. The transmitter end employs a two-stage power amplifier. The receiver end adopts low noise amplifier, Wilkinson power divider, mixer, and variable gain amplifier to retrieve the middle band signals. The middle band signals can be analyzed to conclude information of distance and relative velocity of specified objects by using back-end digital signal processing units. The transmitter in radar system can provide 6 dBm output power with consumption of 120 mW, and single receiver provides 26 dB gain with consumption of 30 mW. The built-in frequency synthesizer has 250 MHz frequency modulation range in FMCW operation consuming 120 mW. The chip area of this radar system is 3.3 mm2 in 40 nm CMOS process.
(II) Wireline transmitter
To exploit the process bandwidth effectively, wireline data transmission evolves with pulse amplitude modulation data format based on conventional NRZ data format. This thesis presents a PAM-8 wireline transmitter on the basis of pulse amplitude modulation techniques. The design includes the high-speed front circuits to drive PAM-8 output signals, and 2-tap feedforward equalizer to compensate the channel loss. On the aspect of testing, the system has built-in digital pseudo random binary sequence generator (PRBS-7, PRBS-15, PRBS-23, PRBS-31), and the data sequence can be serialized to high speed by the multiplexers. The power consumption and the data bandwidth are taken into consideration for circuits operating in different data rate. In addition, to deal with the deviated data sampling point resulted from physical layout and process variation in highspeed operation, a phase alignment circuit is implemented to dynamically ensure the data sampling position. This system supports three output data formats including NRZ, PAM-4, and PAM-8 modulation and can transmit with data rate up to 80 Gbps in single lane transmission consuming 451 mW. This transmitter is implemented in 40 nm CMOS process with area 1.3 mm2.
口試委員會審定書 ...........................................................................................................#
中文摘要 ........................................................................................................................... i
ABSTRACT .................................................................................................................... iii
CONTENTS ......................................................................................................................v
LIST OF FIGURES........................................................................................................ vii
LIST OF TABLES.............................................................................................................x
Chapter 1 Introduction..............................................................................................1
1.1 Motivation.......................................................................................................1
1.2 Organization of the Thesis..............................................................................3
Chapter 2 Design of Radar Transceivers .................................................................4
2.1 Introduction to Automobile Radar Transceivers.............................................4
2.1.1 FMCW Modulation Mechanism ...........................................................4
2.2 Link Budget Analysis .....................................................................................7
2.3 Architecture of the Proposed Transceiver.....................................................10
2.3.1 Transmitter ..........................................................................................12
2.3.2 Receiver...............................................................................................15
2.3.3 Wilkinson Power Divider ....................................................................17
2.3.4 Mixer ...................................................................................................19
2.4 Layout Consideration....................................................................................21
2.5 Measurement Result .....................................................................................22
2.6 Conclusion ....................................................................................................25
Chapter 3 Design of Wireline Transmitter ............................................................27
3.1 Introduction to Serdes...................................................................................27
3.1.1 Comparison of Data Formats ..............................................................28
3.2 Architecture of PAM-8 Transmitter ..............................................................32
3.3 Data Serialization Unit .................................................................................34
3.3.1 PRBS Generation ................................................................................34
3.3.2 Double Edge-triggered Multiplexer ....................................................36
3.3.3 Analog Multiplexer .............................................................................37
3.4 Clock Distribution ........................................................................................40
3.4.1 Clock Buffer and Poly-Phase Filter ....................................................40
3.4.2 Duty Cycle Correction Circuit ............................................................42
3.4.3 Phase Alignment Circuit .....................................................................43
3.4.3.1 Bang-Bang Phase Detector ..................................................44
3.4.3.2 Up/Down Converter and Phase Interpolator ........................45
3.4.3.3 Other Issue ...........................................................................46
3.5 High-speed Frontend ....................................................................................49
3.5.1 Feedforward Equalizer ........................................................................49
3.5.1.1 Implementation of FFE ........................................................52
3.5.2 Pre-driver & Output Combiner ...........................................................53
3.6 Layout Consideration....................................................................................55
3.7 Measurement Result .....................................................................................56
3.8 Conclusion ....................................................................................................62
Bibliography ..................................................................................................................63
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