長久以來，車輛的行車安全一直是人們關心的議題，而近年來交通量的增加，加上自動車的技術逐漸開發，使得在無線通訊領域上，車輛的雷達系統感應及防撞機制又成為了市場關切的需求。
本論文提出了一使用40奈米互補式金屬氧化半導體製程之48GHz多種調變波形之頻率合成器，此頻率合成器與帶隙參考電壓電路、功率放大器、低雜訊放大器、混頻器組成一一發四收之雷達晶片系統。此論文著重於頻率合成器的設計，針對小數型鎖相迴路中的重要電路模組做嚴謹的噪聲分析，並且內建產生各種調變波形之數位電路，以滿足後端雷達系統在不同偵測距離下所需的數位訊號處理資訊。
其頻率合成器的量測結果為在消耗功率為90毫瓦下，其23GHz的時鐘之1MHz偏移頻率下的相位雜訊為-100dBc/Hz，10MHz偏移頻率下的相位雜訊為-115dBc/Hz，並且從100Hz至1GHz積分之方均根時脈抖動為365fs，小數頻率刺小於-59dBc，頻率解析度為119Hz，展頻頻率範圍為250MHz；在雷達系統的量測上，在沒有外部的Sallen-Key濾波器及後端數位訊號處理，僅透過外部收發端天線之增益，並且晶片中的功率放大器提供6分貝毫瓦的功率以及接收器為26分貝的增益情形下，雷達可偵測到之範圍為5公尺以內之目標。

For a long time, the driving safety has always been a topic of concern. In recent years, the increase of traffic volume and the development of automatic car technology have made the radar system sensing and collision avoidance mechanism of the vehicle become market concerns in the field of wireless communication.
This thesis presents a 48GHz frequency synthesizer with multi-modulation waveform applied for 24GHz automotive radar in 40-nm CMOS technology. The 1T4R radar system chipset includes the frequency synthesizer, bandgap reference, power amplifier, low-noise amplifier and mixer. This thesis focuses on the design of frequency synthesizers and does a rigorous noise analysis for important circuit blocks in fractional-N phase-locked loops. With built-in digital circuits for generating various modulated waveforms, the chipset meets the digital signal processing information required by the back-end radar system at different detection distances.
Measurement result shows that the frequency synthesizer of 23GHz carrier achieves the phase noise of -100dBc/Hz at 1MHz offset, -115dBc/Hz at 10MHz offset, 365fs root-mean-square jitter integrated from 100Hz to 1GHz, and below -59dBc fractional spur. Frequency resolution is 119Hz and frequency range of spread spectrum is 250MHz. Without external Sallen-Key filter and back-end digital signal processing, the radar system can detect targets within a range of 5-m only through transceiver antenna, 6dbm power provided by power amplifier and receiver conversion gain of 26dB.

口試委員會審定書 #
中文摘要 i
ABSTRACT ii
CONTENTS iii
LIST OF FIGURES v
LIST OF TABLES viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Thesis 2
Chapter 2 Introduction of Traditional Phase-Locked Loops 3
2.1 Basic Theorem 3
2.2 Problem Discussion 5
Chapter 3 A 48-GHz Low Phase Noise Fractional–N Phase-Locked Loop 9
3.1 Design Consideration 9
3.2 Building Blocks 13
3.2.1 Single-sideband Phase Frequency Detector 13
3.2.2 Operational Transconductance Amplifier Charge Pump 16
3.2.3 Loop Filter 17
3.2.4 LC-tank Voltage Controlled Oscillator 18
3.2.5 Frequency Divider 21
3.3 Phase Noise Analysis 26
3.3.1 VCO Noise Analysis 26
3.3.2 Delta-sigma Modulator Noise Analysis 32
3.3.3 Frequency Divider Noise Analysis 38
3.3.4 Total Phase-Locked Loop Phase Noise Analysis 41
Chapter 4 Multi-Modulation Technique 48
4.1 Introduction of FMCW and MFSK Modulation 48
4.2 Frequency Control Word Circuit 52
Chapter 5 Measurement Results 56
5.1 Set Up 56
5.1 Chip-on-Board Measurement Result 59
Chapter 6 Conclusions 66
REFERENCE 68

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