本論文結合了這五年來，本人與混合信號實驗室之團隊對結合跳躍式演算法 (Skipping Switching Algorithm)與次區間(Subranging)架構的類比數位轉換器(ADC) 之研究，並應用在現今需求量持續增溫的物聯網(IOT)、整合觸控與顯示晶片(TDDI IC) 與億赫茲(GHz)取樣通訊系統中。為了達到低功耗，此篇論文提出了兩種不同的省電切 換方式，分別為切換能量曲線翻轉(Energy-Curve Reshape)技術與重複利用切換(ReSwitching)技術，試圖使應用於觸控感測應用的 ADC 更省電。為了達到高解析度，本論 文也迭代出了兩種應用於雜訊整形(Noise-Shapping)之連續漸進式(SAR) ADC 技術，分 別為殘餘電壓產生技術(Residue Voltage Generate Method)與被動增益多輸入通道震 盪比較器(Passive-Gain Multiple-Input Ring Comparator)，並將解析度推到十三位 元。在節省面積的部分，本論文利用小單位電容搭配權重分裂補償演算(Weight-Split Algorithm)與飄移(Offset)校正，將整體電容陣列大小壓在 KT/C 雜訊的限制，並達到 十四位元的解析度。傳統上，SAR ADC 與其驅動電路結合往往造成驅動電路極大的設計 難度，因此本論文也提出兩種方式，分別為偵測動態開迴路補償系統(Detective OpenLoop Dynamic)簡稱 DeOLD，以及 DeOLD 與穩壓器混合系統，企圖舒緩驅動電路的壓力， 並將電路解析度推到十三位元。在 GHz 取樣通訊系統中，本論文也提出了兩個高速轉換 器的想法，試圖利用無校正的方式將 ADC 的速度拉到 GHz 取樣與十位元之解析度，最後 結合次區間架構並聯四通道的時間交錯(Time-Interleaved) ADC，並加上零點交叉校正 系統(Zero-Crossing Skew Calibration)達到十二位元一億次取樣頻率有低功率的 ADC。 經由十三個實作作品的量測結果，本論文說明了跳躍式演算法加上次區間架構在某些特 定規格上的應用，可以達到品質因數(Figure of Merit)極佳的水準，例如：小面積十 二到十四位元一百萬次取樣(1 MS/s)左右物聯網與觸控應用的 ADC 以及一億次取樣(1 GS/s)二到四通道應用於 GHz 通訊系統的時間交錯 ADC。

This thesis concludes author’s researches in the topic of “the applications of the subranging successive-approximation register (SAR) analog-to-digital (ADC) with the skipping switching method”. The applications includes recently popular internet of things (IOT), touch with driver display integration (TDDI) and giga-hertz (GHz) communication system. Two energy-efficient capacitive digital-to-analog (CDAC) switching methods, namely energy-curve reshape technique and re-switching technique, are presented to makes the ADC more suitable for the touch sensors of the IOT and TDDI applications. This dissertation also proposes two techniques, namely the residue voltage generation method and the passive gain multiple-input ring comparator, for the noise-shapping (NS) architecture with the skipping switching method to increase the resolution up to 13 bits effectively. In terms of shrinking the chip area, the proposed weight-split compensation algorithm successfully combines the energy-efficient skipping switching method with the accurate digital calibration. Hence, the ADC system can maintain high linearity to 14-bit resolution, even the size of the unit capacitor is down to the KT/C limitation. The high-peak dynamic current consumption of the SAR ADC increases the difficulty of the driving system design traditionally. The proposed detective open-loop dynamic (DeOLD) system and the DeOLD hybrid system with an energy-efficient regulator reduce the power consumption of the power system. In addition, it minimizes the size of the decoupling capacitor, which is more suitable for the TDDI system with the zero-capacitor technology. The subranging architecture with the skipping switching method can also be utilized in the ero-crossing skew calibration to achieve low-power 4-channel 12-bit 1 GS/s TI-ADC for the GHz communication system. In conclusion, this dissertation uses thirteen circuit implementation to explain that the subranging architecture with the skipping switching method can achieve better figure of merit (FoM) in certain applications, such as the small area 12-to-14-bit 1 MS/s ADC for IOT sensors and touching sensing of TDDI or 1 GS/s 10-to-12-bit 2-to-4-channels time-interleaved ADC for the GHz communication system.

Chapter 1: Introduction
I. Motivation & Thesis Organization 1
II. Fundamental Specification Definition of ADC 3
A. Offset Error 3
B. Gain Error 4
C. Differential and Integral Nonlinearity (DNL, and INL) 5
D. Signal-to-Noise Ratio (SNR) 5
E. Total Harmonic Distortion (THD) 7
F. Spurious-Free Dynamic Range (SFDR) 7
G. Signal-to-Noise and Distortion Ratio (SNDR) and Effective Number of Bits (ENOB) 8
H. Figure of Merit (FoM) 8
III. Architecture of analog-to-digital converter 9
A. Flash Architecture 10
B. Two-Step and Subranging Architecture 11
C. Pipeline Architecture 11
D. Successive-Approximation Register (SAR) Architecture 12
E. Delta-Sigma Modulation (DSM) ADC 14
F. Incremental ADC 15
G. Time-Interleaved (TI) ADC 16
H. SAR-Based Hybrid Architecture 18
1. Flash-SAR Hybrid Architecture 19
2. Pipeline-SAR Hybrid Architecture 20
3. Noise-Shaping SAR Architecture 22
4. SAR-Assisted Subranging SAR Architecture 23

Chapter 2: Basic Component of SAR ADC
I. Introduction 25
II. Comparator 25
A. Comparator Noise 28
B. Comparator Offset 31
III. Bootstrape 32
A. Clock Feedthrough 33
B. Signal Feedthrough 33
C. Charge Injection 34
D. Speed Consideration 36
E. Sampling Switch Layout Style 36
IV. Capacitive DAC (CDAC) Array 38
A. KT/C Sampling Noise 38
B. Settling Error 39
C. Mismatch 40
D. Layout Style 42
V. CDAC Switching Method 43
VI. SAR Logic 46

Chapter 3: High Resolution Sensor Application
I. Introduction 48
II. Energy-Efficient CDAC Switching Technique 49
A. Energy-Curve Reshape (ECR) Technique 49
1. Architecture 50
2. Proposed ECR Technique 51
3. Polarity Quantizer with Bottom-Plate Sampling 53
4. Pulse-Type Self-Trigger Latch (PT-STL) Technique 55
5. Measurement Results 56
B. Re-Switching (RSW) Technique 57
1. Proposed DAC RSW Technique 58
2. Architecture and Circuit Implementation 60
3. Measurement Results 62
C. CDAC Calibration Technique 64
1. CDAC mismatch weight relation 67
2. Architecture and Circuit Implementation of 12-bit subranging ADC 73
3. Measurement Results of 12-bit subranging ADC 76
4. Offset Calibration for 14-bit Subranging SAR ADC 79
5. Measurement Results of 14-bit subranging ADC 86
III. Noise Suppression Technique 91
A. LSB-Capacitor-Reusing Subranging Architecture 91
1. Proposed Architecture 92
2. Noise Shaping Analysis 94
3. Circuit Implementation 99
4. Experimental Results 104
B. Passive Gain Multiple-Input Ring Comparator 109
1. Proposed Architecture 110
2. Noise Shaping Analysis 112
3. Circuit Implementation 115
4. Experimental Results 120
IV. Conclusion 121

Chapter 4: Zero-Capacitor Column ADC Application
I. Introduction 123
II. DeOLD Compensation Technique 123
A. Proposed DeOLD Concept with Subranging ADC 126
B. Compensation Algorithm 128
C. Charge Compensator 131
D. Circuit Implementation 133
E. Experimental Results 137
F. Conclusion 141
G. Appendix – Derivation of EConv_ideal 141
H. Appendix – Explanation of PSRR 143
III. Hybrid Reference Buffer 146
A. Proposed Hybrid Reference Architecture 146
B. Power Efficient Reference Buffer Circuit Technique 149
1. Accumulated Charge Compensation 149
2. Multi-Gain Stage Dynamic Reference Voltage Stabilizer (RVS) 150
3. VCM Capacitance Reservoir 156
C. Experimental Results 156
IV. Conclusion 157

Chapter 5: High-Speed Communication Application
I. Introduction 159
II. Subranging High Speed Concept 160
A. Advantages of the subranging SAR ADC 161
B. Measurement Results 164
C. Conclusion 166
III. Non-Calibration Skew Suppression Technique 166
A. Proposed 2-Way 2-step SAR ADC with Low-Skew Demultiplexer 167
1. Overall ADC Architecture 167
2. Low-Skew Demultiplexer 169
3. Design Considerations of sub-ADC 170
B. Measurement Result 171
C. Conclusion 173
IV. Zero-Crossing Skew Calibration Method 174
A. Error Sources in TI-ADC 174
1. Offset Mismatch 174
2. Gain Mismatch 175
3. Timing Skew Mismatch 177
B. Defects of a Non-Skew Calibration TI-ADC System 179
1. Prototype Circuit Implementation 180
2. Experimental Results 184
3. Bottleneck and Conclusion 191
C. Skew Calibration TI-ADC System 192
1. Skew Calibration Technique 192
2. Circuit Implementation 200
3. Simulation Results 201
D. Conclusion 203

Chapter 6: Conclusion of this Dissertation
I. Conclusion 204

Reference
I. Reference 205

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