臺灣博碩士論文加值系統

　　此篇論文提出了以無接面金氧半場效電晶體觸發之功率橫向絕緣閘極雙極性電晶體。傳統的絕緣閘極雙極性電晶體中，藉由導通元件的PN二極體，進而有效的降低漂移區的串聯電阻，即為傳導調變效應。但這種功率元件有一個很重要的問題，因為在結構中有寄生的PNPN閘流體，會有閉鎖效應 (Latch-up) 的問題。
　　為了解決閉鎖效應的問題，在本文中，藉由移除元件結構中的P型井後使元件內部沒有寄生的PNPN閘流體。而場效應結構則由無接面金氧半場效電晶體取代了傳統的金氧半場效電晶體。但無接面金氧半場效電晶體會使耐壓特性大幅下降，因此使用溝渠式閘極去薄化無接面電晶體的通道。此外無接面金氧半場效電晶體有更低的導通阻抗。因此以無接面金氧半場效電晶體觸發之絕緣閘極雙極性電晶體解決了閉鎖效應，而且在不會明顯降低耐壓特性的情況下，有更好的導通特性。

　　A lateral insulated-gate bipolar transistor power device triggered by junctionless MOSFET has been proposed. For the conventional IGBT, owing to the conductivity modulation by turning on the pn diode, the large series resistance in the drift can be effectively reduced. However, a major problem with this kind of power device is latch-up because of a parasitic pnpn-thyristor in the device.
　　In order to solve the latch-up problem, IGBT that is without p-well region would not form pnpn structure, and the resultant triggering FET is a junctionless MOSFET instead of a conventional MOSFET. However, the junctionless MOSFET will cause deterioration of breakdown characteristics. For improving the blocking voltage of the device, a trench region is formed to thin the channel region of the junctionless MOSFET. In addition, the junctionless MOSFET can show a lower on-state resistance than the conventional MOSFET. As a result, as compared to the IGBT triggered by a conventional MOSFET, the IGBT triggered by a junctionless MOSFET can resolve the latch-up problem and cause much better on-state characteristics, without obvious degradation of breakdown characteristics.

摘要 i
Abstract ii
致謝 iii
Contents iv
Figure Captions v
Chapter　1 Introduction 1
1-1 Motivation 1
1-2 Conventional power device 1
1-2-1 Power MOSFET 2
1-2-2 IGBT 3
1-3 Device operation 4
1-3-1 Off state 4
1-3-2 On state 4
1-3-3 The problem of the IGBT 4
Chapter　2 Device Fabrication 5
2-1 Junction-less power MOSFET 6
2-2　Junction-less IGBT 7
Chapter　3 Results and Discussion 8
3-1 Conventional power device 8
3-1-1 The off-state electrical characteristic 9
3-1-2 The on-state electrical characteristic 10
3-2 Junction-less power device 12
3-2-1 The off-state electrical characteristic 13
3-2-2 The on-state electrical characteristic 14
3-3 Difference between convention and junction-less power device 16
3-3-1 The off-state electrical characteristic 17
3-3-2 The on-state electrical characteristic 19
3-4 Device parameters adjustment 22
Chapter　4　Conclusion 23
Reference 24

Reference
[1] L. Lorenz "Power semiconductor devices and smart power IC's-the enabling technology for future high efficient power conversion systems," Proceedings of the International Power Electronics and Motion Control Conference, pp. 193-201 (2009).
[2] T. Ogura "Recent technical trends and future prospects of IGBTs and power MOSFETs," Proceedings of the International Power Electronics Conference (IPEC-Hiroshima 2014-ECCE ASIA), pp. 2068-2073 (2014).
[3] B. J. Baliga "Trends in power semiconductor devices," IEEE Transactions on electron Devices, vol. 43, no. 10, pp. 1717-1731 (1996).
[4] O. Spuiber, M. M. De Souza, E.M.S. Narayanan and S. Krishnan "Analyses of a COOL-MOSFET," Proceedings of the International Semiconductor Conference (Cat. No. 99TH8389), vol. 1, pp. 131-134 (1999).
[5] A. Lidow and T. Herman, "High power MOSFET with low on-resistance and high breakdown voltage," US5191396 (1993).
[6] M. H. Chang and P. Rutter "Optimizing the trade-off between the RDS (on) of power MOSFETs and linear mode perfomance by local modification of MOSFET gain," Proceedings of the International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 379-382 (2016).
[7] B. J. Baliga, M. S. Adler, R. P. Love, P. V. Gray and N. D. Zommer "The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device," IEEE Transactions on Electron Devices, vol. 31, no. 6, pp. 821-828 (1984).
[8] L. Benbahouche, A. Merabet and A. Zegadi "A comprehensive analysis of failure mechanisms: Latch up and second breakdown in IGBT (IXYS) and improvement," Proceedings of the International Conference on Microwaves, Radar & Wireless Communications, vol. 1, pp. 190-192 (2012).
[9] C. Toechterle, F. Pfirsch, C. Sandow and G. Wachutka "Analysis of the latch-up process and current filamentation in high-voltage trench-IGBT cell arrays," Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 296-299 (2013).
[10] J. F. Chen, Y. S. Chen, K. S. Tian, K. M. Wu, Y. K. Su, C. M. Liu and S. L. Hsu "Effects of drift-region design on the reliability of integrated high-voltage LDMOS transistors," Proceedings of the International Conference on Integrated Circuit Design and Technology, pp. 1-4 (2007).
[11] A. Kumar, J. K. Sin and V. M. Poon "Drift region doping effects on high voltage conductivity modulated thin film transistors," Proceedings of the IEEE Hong Kong Electron Devices Meeting, pp. 37-40 (1996).
[12] J. Roig, M. Vellvehi, D. Flores, J. Rebollo, J. Millan, S. Krishnan, M. M. De Souza and E. M. S. Narayanan "Analysis of the breakdown voltage in SOI and SOS technologies," Solid-State Electronics, vol. 46, no. 2, pp. 255-261 (2002).
[13] T. Rotter and M. Stoisiek "High-voltage extension (V/sub BR//spl ges/800 V) for smart-power SOI-technologies," Proceedings of the IEEE International Electron Devices Meeting, pp. 447-450 (2004).
[14] T. Trajkovic, N. Udugampola, V. Pathirana, G. Camuso, F. Udrea and G. Amaratunga "800V lateral IGBT in bulk Si for low power compact SMPS applications," Proceedings of the International Symposium on Power Semiconductor Devices & IC's (ISPSD), pp. 401-404 (2013).
[15] M. Badila, X. Jorda, J. Millan, P. Godignon, V. Banu, G. Brezeanu, M. U. Spenea, L. Staicu, E. Iliescu and M. Bazu "A preliminary study on VDMOS and IGBT encapsulation, reliability and lifetime killing," Proceedings of the International Semiconductor Conference (Cat. No. 99TH8389), vol. 1, pp. 55-58 (1999).
[16] L. Dulau, S. Pontarollo, A. Boimond, J. F. Garnier, N. Giraudo and O. Terrasse "A new gate driver integrated circuit for IGBT devices with advanced protections," IEEE Transactions on Power Electronics, vol. 21, no. 1, pp. 38-44 (2006).
[17] B. Baliga, H. Chang, T. Chow and S. Al-Marayati "New cell designs for improved IGBT safe-operating-area," Proceedings of the International Electron Devices Meeting, pp. 809-812 (1988).
[18] N. Patil, D. Das, K. Goebel and M. Pecht "Identification of failure precursor parameters for insulated gate bipolar transistors (IGBTs)," Proceedings of the International conference on prognostics and health management, pp. 1-5 (2008).
[19] E. K. C. Tee, M. Antoniou, F. Udrea, A. Holke, S. J. Pilkington, D.K. Pal, N.L. Yew and W.A.B.W.Z. Abidin "200 V superjunction N-type lateral insulated-gate bipolar transistor with improved latch-up characteristics," IEEE Transactions on Electron Devices, vol. 60, no. 4, pp. 1412-1415 (2013).
[20] S. Takahashi, A. Akio, Y. Youichi, S. Satoshi and N. Norihito "Carrier-storage effect and extraction-enhanced lateral IGBT (E 2 LIGBT): A super-high speed and low on-state voltage LIGBT superior to LDMOSFET," Proceedings of the International Symposium on Power Semiconductor Devices and ICs, pp. 393-396 (2012).
[21] S. M. Lee, C. G. Yu, S. M. Jeong, W. J. Cho, and J. T. Park "Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs," Microelectronics reliability, vol. 52, no. 9-10, pp. 1945-1948(2012).
[22] V. P. Georgiev, A.-L. Dochioiou, F.-A. Lema, S. Berada, M. M. Mirza, D. J. Paul and A. Asenov "Variability study of high current junctionless silicon nanowire transistors," Proceedings of the Nanotechnology Materials and Devices Conference (NMDC), pp. 87-88(2017).
[23] R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-Orabi and K. Kuhn "Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm," IEEE electron device letters, vol. 32, no. 9, pp. 1170-1172(2011).
[24] J.-P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazarov and R. T. Doria "Reduced electric field in junctionless transistors," Applied Physics Letters, vol. 96, no. 7, p. 073510(2010).
[25] W. Wan, H. Lou, Y. Xiao, and X. Lin "The immunity of doping-less junctionless transistor variations including the line edge roughness," Proceedings of the International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 66-69(2016).
[26] R. Trevisoli, R. T. Doria, M. de Souza, S. Barraud, M. Vinet, and M. A. Pavanello "A new series resistance extraction method for junctionless nanowire transistors," Proceedings of the Symposium on Microelectronics Technology and Devices (SBMicro), pp. 1-4(2016).
[27] G. Jawade, Y. Chavan, and S. Wagaj "High performance dual spacer double gate junctionless transistor for digital integrated circuits," Proceedings of the International Conference on Inventive Computation Technologies (ICICT), vol. 2, pp. 1-4(2016).
[28] M. de Souza, R. Doria, R. Trevisoli, and M. Pavanello "Ultra-low-power diodes using junctionless nanowire transistors," Proceedings of the International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, pp. 313-316(2015)