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研究生:郭信甫
研究生(外文):Shin-Fu Guo
論文名稱:應用線性混頻器技術實現雙電容性共振腔注入鎖定除頻器
論文名稱(外文):Double Capacitive Cross-Coupled Injection Frequency Divider Using Linear Mixer Approach
指導教授:張勝良
指導教授(外文):Sheng–Lyang Jang
口試委員:馮武雄賴文政宋峻宇
口試委員(外文):Wu-Shiung FengWen-Cheng LaiJiun-Yu Sung
口試日期:2019-07-29
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:英文
論文頁數:129
中文關鍵詞:壓控振盪器注入鎖定除頻器線性混頻器交叉耦合鎖頻範圍
外文關鍵詞:Voltage Controlled OscillatorInjection-Locked Frequency DividerLinear MixerCross-CoupledLocking Range
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射頻積體電路(RFIC)中,收發器(Transceiver)的鎖相迴路(Phase locked loop)特性格外的重要,PLL內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD),而為了追求低功耗,低相位雜訊,與較寬的除頻範圍,在這其中又以壓控振盪器和注入鎖定除頻器特性最重要,而此論文主要研究鎖相迴路中的注入鎖定除頻器。

首先,第一部分我們呈現一個寬頻除六注入鎖定除頻器,此除頻器使用台積電矽鍺0.18 μm製程,晶片面積為855.42×954.492 μm2。此除三除頻器設計基於一電容耦合的壓控振盪器,且再外加一個共振腔來增加除頻範圍,可以找到除頻器最寬可除頻範圍在13.2 GHz ~ 16 GHz (21.02%)。但此除頻器最佳工作電壓操作在0.95伏特,整體功耗為5.6 mW,在注入強度為0 dbm時,除頻範圍可從14.5 GHz ~ 16.3 GHz (11.69%),FOM為2.09。
接著,第二部份我們呈現一個寬頻除五注入鎖定除頻器,由電矽鍺0.18 μm製程實現。此除五除頻器也是使用雙電容性共振腔的架構。在工作偏壓0.95 V、注入強度0 dBm下,除五範圍總共為3.8 GHz,注入頻率從12 GHz ~ 15.8 GHz,總除頻百比例為27.34 %。此除頻器功耗為5.11 mW,晶片面積855.42×954.492 μm2。

接著,第三部份我們呈現一個寬頻除四注入鎖定除頻器,同樣使用電矽鍺0.18 μm製程來實現。此除頻器使用使用雙電容性共振腔的架構下設計,而這次特別使用一對自製互感結合可調式電容以移動除頻範圍。在VT的調整下,可使互感的強度增加進而影響除頻範圍移動,形成一個彈性較高的除頻器。在驅動偏壓為0.95 V、注入功率為0 dbm時,注入鎖定頻率為10.1 ~ 14 GHz,鎖住範圍共3.9GHz,百分比為32.37 %。此晶片面積為1006.28 × 925.377 μm2,除頻器的核心功耗共2.61 mW。

最後,第四部份我們呈現一個雙共振腔除三注入鎖定除頻器,同樣使用電矽鍺0.18 μm製程來實現。此除三除頻器也是使用雙電容性共振腔的架構。在工作偏壓0.9 V、注入強度0 dBm下,除五範圍總共為4.7 GHz,注入頻率從6.3 GHz ~ 11 GHz,總除頻百比例為54.33 %。此除頻器功耗為4.45 mW,晶片面積855.42×954.492 μm2。
In the RF integrated circuits (IC) , PLL are very important block of the transceiver circuit, PLL characteristics include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide Locking range, the most important characteristics of performance are VCO and Divider, this thesis presents the design of Injection-locked frequency dividers (ILFDs).

First, a Wide-Locking Range Divide-by-6 Injection-Locked Frequency Divider Using Linear Mixer Approach (ILFD) using a standard 0.18 μm BiCMOS process is presented. The die area is 855.42×954.492 μm2. The ILFD circuit bases on capacitive cross-coupled oscillator and uses extra capacitive cross-coupled to enhance the locking range , therefore we found maximum locking range at 13.2 GHz ~ 16 GHz (19.86%). But the best performance of the chip is at supply voltage 0.95 V, the power consumption of the ILFD core is 5.6 mW and the locking range is from 14.5 GHz ~ 16.3 GHz (11.69%) at injection power Pinj = 0 dBm.

Secondly, a 5:1 LC-resonator Injection-Locked Frequency Dividers (ILFD) was implemented in the standard 0.18 μm BiCMOS process. The divide-by-5 ILFD uses double capacitive cross-coupled oscillator. At the power supply of 0.95 V, and at the incident power of 0 dBm the maximum locking range of the divide-by-5 ILFD is 3.8 GHz (27.34%) from 12 to 15.8 GHz, the ILFD has overlapped locking ranges. The core power consumption is 5.11 mW. The die area is 855.42×954.492 μm2.

Third, a Wide-Band Harmonic Mixer Divide-by-4 Injection-Locked Frequency Divider (ILFD) was implemented in the standard 0.18 μm BiCMOS process. The divide-by-4 ILFD uses double capacitive cross-coupled oscillator and mutual inductors combine with a pair of varactors. At the power supply of 0.95 V, and at the incident power of 0 dBm, the locking range of the divide-by-4 ILFD is 3.9 GHz, from the incident frequency 10.1 to 14 GHz and the locking range percentage is 32.37%. The die area is 1006.28 × 925.377 μm2. The power consumption of ILFD core is 2.61 mW.

Finally, a Double Capacitive Cross-Coupled Divide-by-3 Injection-Locked Frequency Divider (ILFD) was implemented in the standard 0.18 μm BiCMOS process. The divide-by-3 ILFD uses double capacitive cross-coupled oscillators. At the power supply of 0.9 V, and at the incident power of 0 dBm the maximum locking range of the divide-by-3 ILFD is 4.7 GHz (54.33%) from 12 to 15.8 GHz, the ILFD has overlapped locking ranges. The core power consumption is 4.45 mW. The die area is 855.42×954.492 μm2.
摘要 I
Abstract III
致謝 V
Table of Contents VI
List of Figures IX
List of Tables XV
Chapter 1 Introduction 1
1.1 Background 1
1.2 Thesis Organization 3
Chapter 2 Principles and Design Considerations of Voltage Controlled Oscillators 5
2.1 Introduction 5
2.2 Basic concepts 7
2.2.1 Feedback Oscillators 7
2.2.2 Resonator and Negative Resistance 9
2.3 The Classification of Oscillators 12
2.3.1 Ring Oscillator 12
2.3.2 LC-Tank Oscillator 15
2.4 Passive Components Design in VCO 24
2.4.1 Inductor Design 24
2.4.2 Transformer Design 27
A. Physical Layouts of Transformers 29
B. Compact Models of Transformer 33
2.4.3 Capacitor Design 35
2.4.4 Varactor Design 37
2.4.5 Resistor Design 41
2.5 The Performance parameters of VCO 42
2.5.1 RF Center Frequency [Hz] 42
2.5.2 RF Output Signal Power [dBm] 42
2.5.3 Power Dissipation [mW] 42
2.5.4 Harmonic/spurious [dBc] 43 Phase Noise 43
2.5.6 Tuning Range 46
2.5.7 Tuning Sensitivity [Hz/V] 47
2.5.8 Quality Factor 48
2.5.9 Figure of Merit [dBc/Hz] 51
Chapter 3 Design of Injection Locked Frequency Divider 52
3.1 General considerations 53
3.2 Operation Range 55
Chapter 4 Wide-Locking Range Divide-by-6 Injection-Locked Frequency Divider Using Linear Mixer Approach 60
4.1 Introduction 60
4.2 Circuit Design 63
4.3 Measurement Results 68
Chapter 5 5:1 LC-resonator Injection-Locked Frequency Dividers 74
5.1 Introduction 74
5.2 Circuit Design 75
5.3 Measurement Results 79
Chapter 6 Wide-Band Harmonic Mixer Divide-by-4 Injection-Locked Frequency Divider 85
6.1 Introduction 85
6.2 Circuit Design 86
6.3 Measurement Results 88
Chapter 7 Double Capacitive Cross-Coupled Divide-by-3 Injection-Locked Frequency Divider 95
7.1 Introduction 95
7.2 Circuit Design 96
7.3 Measurement Results 97
Chapter 8 Conclusions 103
References 105
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