臺灣博碩士論文加值系統

本論文提出具中心抽頭電感雙輸出之降壓型轉換器，一般單電感多輸出是使用傳統電感器，主要特色以中心抽頭電感延長責任週期達到更大的降壓比，並利用延長責任週期降低上臂功率級開關峰值電流改善切換損，將電感電流操作在連續導通模式，並利用相序調整方式來抑制交叉穩壓現象。
本論文採用TSMC 0.35 m 2P4M 3.3/5 V mixed-signal CMOS製程實現，晶片包含PADs之晶片面積為1.7×3.342 mm2。輸入電壓為5 V，輸出電壓分別為1.8 V及1.2 V，輸出負載範圍各為50-400 mA，外接功率級中心抽頭電感為4.7 H匝數比為1.5，輸出電容為10 F。模擬結果交叉穩壓為0.125-0.175 mV/mA，轉換器最高效率在兩輸出各100 mA為92.3%，最低效率在兩輸出各400 mA為89%。

This thesis proposes a dual-output voltage mode buck with a tapped inductor. The general single-inductor multi-output uses a traditional inductor. The main feature of this paper is to extend the duty cycle of the tapped inductor to achieve a larger step-down ratio, and to extend the responsibility. The extend cycle reduces the peak current of the upper power stage switch to improve the switching loss, operates the inductor current in continuous conduction mode, and uses phase sequence scheme to suppress the cross regulation phenomenon.
This thesis is implemented in the TMSC 0.35 m 2P4M 3.3/5 V mixed-signal CMOS process. The wafer area of the wafer containing PADs is 1.7×3.342 mm2. The input voltage is 5 V, the output voltage is 1.8 V and 1.2 V respectively, the output load range is 50-400 mA, the external power stage tapped inductance is 4.7 H, the turns ratio is 1.5, and the output capacitance is 10 F. The simulation results have a cross-regulated voltage of 0.125-0.175 mV/mA. The maximum efficiency of the converter is 92.3% for each of the two outputs of 100 mA, and the lowest efficiency is 89% for each of the two outputs of 400 mA.

摘　要 iv
Abstract v
誌　謝 vi
圖索引 xi
表索引 xv
第一章 緒論 1
1.1 研究動機與目的 1
1.2 論文內容架構 3
第二章 單電感多輸出電路架構與控制方法 4
2.1 單電感多輸出轉換器簡介 4
2.2 單電感多輸出轉換器工作原理 5
2.2.1 單電感多輸出降壓型轉換器 5
2.2.2 單電感多輸出升壓型轉換器 6
2.2.3 單電感多輸出升降壓型轉換器 6
2.3 單電感多輸出轉換器操作模式 8
2.3.1 分時多工控制 8
2.3.2 偽連續導通模式 16
2.3.3 能量分佈控制 23
2.4 交叉穩壓 30
第三章 具中心抽頭電感雙輸出之降壓型轉換器 31
3.1 中心抽頭電感降壓器架構 31
3.1.1 中心抽頭電感降壓器作動 32
3.1.2 中心抽頭電感降壓器轉換比 34
3.1.3 雙輸出中心抽頭電感設計 36
3.2 回授控制電路 40
3.2.1 相序調整技術 40
3.2.2 電壓模式回授控制 41
第四章 轉換器設計與實現 45
4.1 系統整體架構簡介 45
4.2 內部電路設計 47
4.2.1 鋸齒波產生器 47
4.2.2 磁滯比較器 48
4.2.3 二級放大器 48
4.2.4 死區時間 49
4.2.5 相序調整電路 51
第五章 模擬結果與電路佈局 52
5.1 內部電路模擬波形 52
5.1.1 鋸齒波產生器 52
5.1.2 磁滯比較器 52
5.1.3 二級放大器 53
5.1.3 死區時間 54
5.2 具中心抽頭電感雙輸出之降壓型轉換器之模擬波形 55
5.2.1 模擬軟體Simplis模擬結果 55
5.2.2 模擬軟體Spectre模擬結果 56
5.2.3 模擬結果比較 58
5.3 晶片佈局圖 61
5.4晶片腳位配置與定義 63
第六章 實測波形 65
第七章 結論與未來展望 68
參考文獻 70

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