跳到主要內容

臺灣博碩士論文加值系統

(44.192.49.72) 您好!臺灣時間:2024/09/18 20:54
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:巫偉豪
研究生(外文):Wei-Hao Wu
論文名稱:基於TLC快閃記憶體之保留錯誤緩解方法
論文名稱(外文):A Retention-Error Mitigation Method based on TLC NAND Flash Memory
指導教授:吳晋賢
指導教授(外文):Chin-Hsien Wu
口試委員:吳晋賢林昌鴻林淵翔陳維美
口試委員(外文):Chin-Hsien WuChang-Hong LinYuan-Hsiang LinWei-Mei Chen
口試日期:2019-08-15
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:63
中文關鍵詞:快閃記憶體三階儲存單元可靠度保留錯誤
外文關鍵詞:NAND flashtriple-level cell (TLC)reliabilityretention error
相關次數:
  • 被引用被引用:1
  • 點閱點閱:219
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
由於快閃記憶體具有有限的編程/抹除次數(P/E cycles)限制,通常在超過該上限次數後,逐漸不堪使用,而其核心原因來自於快閃記憶體單元內的寫穿(wear-out)現象,在此現象的影響下,任何資料在快閃記憶體中都僅能在有限的時間內安全儲存,並隨著資料的保留時間增加,保留錯誤率持續上升,最終錯誤率超過ECC可糾錯能力而損壞。由於保留錯誤是快閃記憶體的主要錯誤,而其錯誤率又和不同狀態間存在相依的現象,建立在此基礎之上,現今有一些保留錯誤的緩解方法被提出,本文提出了一種在TLC快閃記憶體單元內的寫入頁面配置方法WPS以及字線寫入區塊分類WBC機制,前者的方案是以之前方法的權重計算為基礎,去設計一種新的編碼方式並且包括了新的Flag設計以及狀態編碼的優化;而後者是一種新的耗損平均機制,透過這二種新的方法可以減少保留錯誤率外並增加各個區塊的壽命。
Since NAND flash memory has limited P/E cycles, it could be unusable after exceeding the limited P/E cycles, and the main reason is the wear-out phenomenon in the flash memory cell. Under the influence of this phenomenon, any data can only be safely stored in the flash memory for a limited time (i.e., the retention time). As the retention time increases, the retention error rate continues to rise, and the final retention error rate could exceed the ECC capability. Since the retention error is the main error of the flash memory and its error rate is dependent on different states, some mitigation methods for retention errors are proposed. In the thesis, we propose a retention error mitigation method based on TLC NAND flash memory. The proposed method contains a write position selection scheme (including a new flag design and state coding optimization) and a word-line block classification mechanism for the wear-leveling issue. According to the experimental results, we can reduce the retention error rate and increase the lifetime of TLC NAND flash memory.
第一章 緒論 1
1.1 前言 1
1.2 論文架構 1
第二章 環境背景 2
2.1 NAND Flash Memory 2
2.2 NAND Flash Memory Organization 2
2.3 SLC、MLC、TLC架構 3
2.4 Architecture Restriction 4
2.5 Flash Translation Layer 5
2.6 ECC 6
2.7 Data Retention Errors 7
2.8 Bit-Flip Strategy 8
2.9 Refresh Mechanisms 9
2.10 Bad Block Management 10
第三章 研究動機與相關研究 12
3.1 研究動機 12
3.2 相關研究 13
第四章 基於TLC快閃記憶體的保存錯誤緩解 16
4.1 概述 16
4.2 Write Position Selection 18
4.2.1 Flag映射表設計 19
4.2.2 WPS狀態權重設計與權重計算 20
4.2.2.1 資料保留錯誤率推估方法 23
4.2.3 狀態編碼的優化設計 24
4.3 Word-line Block Classification 24
第五章 實驗與效能分析 30
5.1 實驗環境 30
5.2 實驗負載 31
5.3 實驗結果 33
5.3.1 工作負載的組成與分析 33
5.3.2 保留錯誤率分析 38
5.3.3 Word-line Block Classification保留錯誤率分析 44
第六章 結論 49
第七章 參考文獻 50
[1] Y. Takai, M. Fukuchi, R. Kinoshita, C. Matsui, and K. Takeuchi, “Analysis on heterogeneous ssd configuration with quadruple-level cell (qlc) nand flash memory,” in 2019 IEEE 11th International Memory Workshop (IMW), May 2019, pp. 1–4.
[2] Y. Cai, G. Yalcin, O. Mutlu, E. F. Haratsch, A. Cristal, O. S. Unsal, and K. Mai, “Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime,” in 2012 IEEE 30th International Conference on Computer Design (ICCD), Sep. 2012, pp. 94–101.
[3] S. Tanakamaru, C. Hung, and K. Takeuchi, “Highly reliable and low power ssd using asymmetric coding and stripe bitline-pattern elimination programming,” IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 85–96, Jan 2012.
[4] Y. Deguchi and K. Takeuchi, “Word-line batch vth modulation of tlc nand flash memories for both write-hot and cold data,” in 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov 2017, pp. 161–164.
[5] O. Mutlu and T. Moscibroda, “Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared dram systems,” SIGARCH Comput. Archit. News, vol. 36, no. 3, pp. 63–74, Jun. 2008. [Online]. Available: http://doi.acm.org/10.1145/1394608.1382128
[6] ADVANTECH, company, Tech. Rep., 2016.
[7] Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, and E. F. Haratsch, “Vulnerabilities in mlc nand flash memory programming: Experimental analysis, exploits, and mitigation techniques,” in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb 2017, pp. 49–60.
[8] J. Park, J. Jeong, S. Lee, Y. Song, and J. Kim, “Improving performance and lifetime of nand storage systems using relaxed program sequence,” in 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), June 2016, pp. 1–6.
[9] J.-U. Kang, J.-S. Kim, C. Park, H. Park, and J. Lee, “A multi-channel architecture for high-performance nand flash-based storage system,” J. Syst. Archit., vol. 53, no. 9, pp. 644–658, Sep. 2007. [Online]. Available: http://dx.doi.org/10.1016/j.sysarc.2007.01.010
[10] A. Gupta, Y. Kim, and B. Urgaonkar, “Dftl: A flash translation layer employing demand-based selective caching of page-level address mappings,” SIGPLAN Not., vol. 44, no. 3, pp. 229–240, Mar. 2009. [Online]. Available: http://doi.acm.org/10.1145/1508284.1508271
[11] D. Park, B. Debnath, and D. Du, “Cftl: A convertible flash translation layer adaptive to data access patterns,” in Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, ser. SIGMETRICS ’10. New York, NY, USA: ACM, 2010, pp. 365–366. [Online]. Available: http://doi.acm.org/10.1145/1811039.1811089
[12] Jesung Kim, Jong Min Kim, S. H. Noh, Sang Lyul Min, and Yookun Cho, “A space-efficient flash translation layer for compactflash systems,” IEEE Transactions on Consumer Electronics, vol. 48, no. 2, pp. 366–375, May 2002.
[13] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song, “A log buffer-based flash translation layer using fully-associative sector translation,” ACM Trans. Embed. Comput. Syst., vol. 6, no. 3, Jul. 2007. [Online]. Available: http://doi.acm.org/10.1145/1275986.1275990
[14] H. Cho, Dongkun Shin, and Y. I. Eom, “Kast: K-associative sector translation for nand flash memory in real-time systems,” in 2009 Design, Automation Test in Europe Conference Exhibition, April 2009, pp. 507–512.
[15] S. Lee, D. Shin, Y.-J. Kim, and J. Kim, “Last: Locality-aware sector translation for nand flash memory-based storage systems,” SIGOPS Oper. Syst. Rev., vol. 42, no. 6, pp. 36–42, Oct. 2008. [Online]. Available: http://doi.acm.org/10.1145/1453775.1453783
[16] A. C. Patthak, “Error correcting codes: Local testing, list decoding, and applications,” Ph.D. dissertation, Austin, TX, USA, 2007, aAI3290894.
[17] Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, “Error characterization, mitigation, and recovery in flash-memory-based solid-state drives,” Proceedings of the IEEE, vol. 105, no. 9, pp. 1666–1704, Sep. 2017.
[18] Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu, “Improving 3d nand flash memory lifetime by tolerating early retention loss and process variation,” in Abstracts of the 2018 ACM International Conference on Measurement and Modeling of Computer Systems, ser. SIGMETRICS ’18. New York, NY, USA: ACM, 2018, pp. 106–106. [Online]. Available: http://doi.acm.org/10.1145/3219617.3219659
[19] K. Mizoguchi, T. Takahashi, S. Aritome, and K. Takeuchi, “Data-retention characteristics comparison of 2d and 3d tlc nand flash memories,” in 2017 IEEE International Memory Workshop (IMW), May 2017, pp. 1–4.
[20] Y. Pan, G. Dong, Q. Wu, and T. Zhang, “Quasi-nonvolatile ssd: Trading flash memory nonvolatility to improve storage system performance for enterprise applications,” in IEEE International Symposium on HighPerformance Comp Architecture, Feb 2012, pp. 1–10.
[21] X. Jimenez, D. Novo, and P. Ienne, “Wear unleveling: Improving NAND flash lifetime by balancing page endurance,” in Proceedings of the 12th USENIX Conference on File and Storage Technologies (FAST 14). Santa Clara, CA: USENIX, 2014, pp. 47–59. [Online]. Available:https://www.usenix.org/conference/fast14/technicalsessions/presentation/jimenez
[22] Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, “Data retention in mlc nand flash memory: Characterization, optimization, and recovery,” in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), Feb 2015, pp. 551–563.
[23] 48GB TLC NAND flash memory, Micron Technology, mT29F384G08EBCBBJ4.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊