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研究生:陳劭
研究生(外文):Shao Chen
論文名稱:應用於5G天線陣列波束調相之400MHz 16相位精確時脈產生電路
論文名稱(外文):Precise 16 phases 400MHz clock generator for 5G beam steering
指導教授:姚嘉瑜
指導教授(外文):Chia-Yu Yao
口試委員:陳筱青彭盛裕
口試委員(外文):Hsiao-Chin ChenSheng-Yu Peng
口試日期:2019-7-17
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:中文
論文頁數:91
中文關鍵詞:16 相位時脈產生電路四相位壓控震盪器注入鎖定除頻器
外文關鍵詞:16 phases clock generatorQuadrature voltage controlled oscillatorInjection locked frequency divider
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本論文主要針對天線陣列中波束調相技術進行先期的研究。根據系統要求必須產生頻率為400 MHz的16相位時脈,為了提供天線陣列系統準確且高品質的16相位控制信號,我們提出利用鎖相迴路先將較易取得的100 MHz參考輸入信號升頻至1600 MHz,利用四相位電壓控制震盪器產生頻率為1600 MHz的正交四相位信號,再以鎖相迴路產生的正交四相位信號作為注入式鎖定除頻器的注入信號,降頻並分出頻率為400 MHz 的等相差16相位時脈,以上為本論文提出的應用於5G天線陣列波束調相之400 MHz 16相位精確時脈產生電路。
在本論文提出的系統中,我們先利用鎖相迴路作為頻率合成器將100 MHz輸入參考信號升頻至1600 MHz,其中,鎖相迴路架構包含:相位頻率偵測器、動態電流補償充電泵、四相位壓控震盪器,以及回授除法器。考量系統需求,為了要產生精準且低相位雜訊的16相位時脈,一般的環型震盪器或難以達到,因此我們提出利用LC-tank架構的四相位壓控震盪器產生準確且低相位雜訊的輸出信號,再經由注入鎖定除頻器產生16相位輸出信號。本論文提出的注入鎖定除頻器乃是利用高品質的注入信號帶動基於環型震盪器的四級差動對架構,由此產生相應的16相位信號輸出。
本論文設計晶片採用TSMC 90nm CMOS製程實現,晶片內電路全部採用Full-Custom設計流程實現。其中鎖相迴路鎖定之頻段範圍為1.525 GHz至1.7 GHz,輸入參考時脈100 MHz,系統輸出400M Hz 相差22.5˚的16相位信號。系統核心操作功率消耗約為32.69m W,晶片面積約為2.6 〖mm〗^2。
This thesis mainly focuses on the early research of beam steering technique for antenna array system. According to the system specification, we have to generate 16 signals with equal phase differences at 400 MHz. In order to provide highly accurate 16-phase control signals for the antenna array, we propose use a Phase Locked Loop (PLL) up-convert the 100 MHz reference clock to 1.6 GHz, then using a Injection Locked Frequency Divider (ILFD) to down-convert the output signals of the Quadrature- Voltage Controlled Oscillator (Q-VCO) to 400 MHz to generate 16 clocks with equal phase differences at the same time. This is the proposed “Precise 16 phases 400MHz clock generator for 5G beam steering” for this thesis.
In the proposed system, we first utilize the PLL as a frequency synthesizer to up-convert the 100 MHz reference clock to 1.6 GHz. The PLL is composed of 4 different blocks, including a Phase Frequency Detector (PFD), a Charge Pump (CP), a Quadrature- Voltage Controlled Oscillator (Q-VCO), and a frequency divider. According to the system specification, the phase difference between the 16-phase control signals has to be very precise at 22.5˚ degree. A conventional ring oscillator cannot provide signals with such highly precise phase difference. Thus, we employ an LC- tank Q-VCO to generate accurate and low phase noise output signals, then use the ILFD to generate the 16 phases output. The ILFD we used, has a 4- stage differential structure with high quality quadrature injecting signals, the ILFD can generate 16-phase output clocks.
The chip is fabricated in TSMC 90nm CMOS process technology. The frequency tuning rang of the PLL is from 1.525 GHz to 1.7 GHz. The frequency of the input reference is 100 MHz, the output 16 phases have equal phase difference of 22.5˚ at 400 MHz. The core power consumption is approximately 32.69 mW, and the chip size is approximately 2.6 〖mm〗^2.
摘要………………………………………………………………………………I
Abstract ……………………………………………………..…………………II
誌謝……………………………………………………………………………III
目錄…………………………………………………………………………….IV
圖目錄…………………………………………………..…………………..VIII
表目錄…………………………………………………………………………XI
第一章 緒論 ………………………………………………………..…………..1
1-1 研究動機………………………………………………………….…………...1
1-2 論文規劃………………………………………………………….…………...4
第二章 鎖相迴路介紹與設計考量 …………………………………….……5
2-1 鎖相迴路介紹………………………………………………………………...5
2-1.1 類比式鎖相迴路……………………………………………………….5
2-1.2 電荷幫浦式鎖相迴路………………………………………………….6
2-1.3 全數位式鎖相迴路…………………………………………………….7
2-1.4 系統應用……………………………………………………………….9
2-2 鎖相迴路設計考量 ………………………………………………………….10
2-2.1 相位雜訊…………………………………………………...…………10
2-2.2 突波…………………………………………………………………...11
2-2.3 鎖定時間……………………………………………………………...11.
第三章 應用於5G天線陣列波數調相之400 MHz 16相位時脈產生電路系統架構介紹與模擬. ……………………………………………………………………..13
3-1 系統架構 …………………………………………………………………….13
3-2 相位頻率偵測器……………………………………………………………..15
3-3 電荷幫浦…………………………………………………………………….19
3-4 迴路濾波器…………………………………………………………………25
3-5 四相位電壓控制震盪器…………………………………………………...30
3-6 除頻器……………………………………………………………………….40
3-7 注入式鎖定除頻器………………………………………………………...44
第四章 晶片佈局與量測結果……………………………………………… 49
4-1 晶片設計流程………………………………………………………………..50
4-2 晶片佈局規劃 ……………………………………………………………….51
4-3 量測環境 …………………………………………………………………….52
4-4 量測結果 …………………………………………………………………….54
4-4.1 四相位壓控震盪器…………………………………………………...54
4-4.2 注入鎖定除頻器……………………………………………………...61
4-4.3 鎖相迴路……………………………………………………………...63
4-4.4 量測結果總結………………………………………………………...69
4-5 晶片規格與文獻比較………………………………………………………..70

第五章 結論與未來展望 …………………………………………………….72
5-1 結論………………………………………………………………………….72
5-2 未來展望…………………………………………………………………….73
參 考 文 獻 ………………………………………………………………….74
Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yeu Wu, “A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm,” IEEE Transaction on Circuits and Systems- II: Exp. Briefs, vol. 57, no. 6, pp. 430-434, June 2010.
Paolo Rocca and Giacomo Oliveri, Robert J Mailloux, Andrea Massa, “Unconventional phased array architectures and design methodologies-A Review,” Proceedings of the IEEE, vol. 104, no. 3, pp. 544-560, March 2016.
L.C. Godara, “Application of antenna arrays to mobile communications, part II: beam-forming and direction-of-arrival considerations,” Proceedings of the IEEE, vol. 85, no. 8, pp. 1195-1245, August 1997.
William F. Moulder, Waleed Khalil, John L. Volakis, “60-GHz two-dimensionally scanning array employing wideband planar switched beam network,” IEEE Antennas and Wireless Propagation Letters, vol. 9, pp. 818-821, August 2010.
Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu, “A shifted-averaging VCO with precise multiphase outputs and low jitter operation,”29th European Solid-State Circuits Conference, Estoril, Portugal, September 2004, pp 647-650.
Roland E. Best, Phase Locked Loops: Design, Simulation, and Applications, 3rd Edition. Singapore: McGraw-Hill., 1993.
廖煥森, Low-Power Phase-Locked Loop Design. M.S. Thesis, Tamkung University, 1999.

C.-C. Cheng, The analysis and design of all digital phase-locked loop (ADPLL). M.S. Thesis, National Chiao-Tung University, 2001.
T.H. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 326-336, March 2000.
Patrik Larsson, Christer Svensson, “Impact of clock slope on true single phase clocked (TSPC) CMOS circuits,” IEEE Journal of Solid-State Circuit, vol. 29, no. 6, pp. 723-726, June 1994.
Tsung-Hsien Lin, Ching-Lung Ti, and Yao-Hong Liu, “Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs,” IEEE Transactions on Circuits and System-I: Regular Papers, vol. 56, no. 5, pp. 877-885, May 2009.
劉深淵, 楊清淵, 鎖相迴路. 滄海書局, 2006.
Ping-Yi Wang, Yin-Cheng Chang, Kai-Hsin Chung, Da-Chiang Chang, and Shawn S. H. Hsu, “A low phase-noise 24GHz CMOS quadrature-VCO using PMOS-source-follower coupling technique,” Proceedings of the 44th European Microwave Conference, Oct. 2014, pp 572-575.
Hye-Ryoung Kim, Choong-Yul Cha, Seung-Min Oh, Moon-Su Yang, Sang-Gug Lee, “A very low-power quadrature VCO with back-gate coupling,” IEEE Journal of Solid-State Circuits, vol. 39, no. 6, pp. 952-955, June 2004.
Ali Hajimiri, Thomas H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999.

J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
Behzad Razavi, “The cross-coupled pair-part I,” IEEE Solid-State Circuits Magazine, vol. 9, no. 3, pp. 7-10, Summer 2014.
Supeng Liu, Yuanjin Zheng, Wei Meng Lim, Wanlan Yang, “Ring oscillator based injection locked frequency divider using dual injection paths,” IEEE Microwave and Wireless Components Letters, vol. 25, no. 5, pp. 322-324, May 2015.
Shu-You Lin and Hwann-Kaeo Chiou, “A modified high phase accuracy SIC-QVCO using a complementary-injection technique,” IEEE Microwave and Wireless Components Letters, vol. 29, no. 3, pp. 222-224, March 2019.
Meng-Han Li, Yen-Han Liao, Hong-Yeh Chang, “A K-band low power high accuracy quadrature VCO using gate-modulated coupling and transformer feedback technique,” Proceeding of Asia-Pacific Microwave Conference, Sendai, Japan, Nov. 2014, pp. 895-897.
Md. Tawfiq Amin, Pui-In Mak, Rui P. Martins, “A 0.137 〖mm〗^2 9 GHz hybrid class-B/C QVCO with output buffering in 65nm CMOS,” IEEE Microwave and Wireless Components Letters, vol. 24, no.10, pp. 716-718, October 2014.
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