臺灣博碩士論文加值系統

長久以來，內建自我修復技術與錯誤修正碼是時常被拿來保護記憶體的技術，用以提升記憶體的良率與可靠度，然而它們彼此的功用卻不相同。一般來說內建自我修復技術是用在修復流程以修復硬錯誤，錯誤修正碼是用在記憶體正常操作模式下，以修復軟錯誤，而近年來錯誤修正碼也漸漸地被使用在修復階段，以提升記憶體的良率。瑕疵一般都是隨機落在記憶體陣列上，而採用內建自我修復技術修復記憶體時，單一備用元件能修復的故障細胞往往有限，為了達到高修復率，需要足夠數量的備用元件，若數量不足的話，則內建自我修復的修復會失敗。
為了解決此缺點，基於位址重映射的故障群集技術在此篇被提出，用以在內建備用分析之前先改變記憶體陣列裡故障細胞的邏輯位址，使故障細胞彼此落在同個列或是同個字上，如此一來可以提升備用元件能修復故障細胞，也可進一步提升記憶體良率，而本篇也採用錯誤修正碼修復剩餘的故障細胞，可使得良率再往上提升。為了實現故障群集技術，易實現於電路的啟發式 (Heuristic) 的故障群集演算法被提出，故障群集演算法會依序 (Sequential) 地改變每個記憶體區塊的邏輯位址，使記憶體區塊與區塊之間的故障細胞能達成上述之群集效果，其架構可以容易地與內建自我修復技術的電路做結合。除此之外，本篇開發了用於模擬修復率的模擬器和推估硬體成本的模型，而根據實驗結果，本篇提出之故障群集技術可以大幅提升修復率且其產生之硬體成本只增加不到2%。

Built-in self-repair (BISR) techniques and error correction code (ECC) have been widely used for improving the yield and reliability of embedded memories. The main targets of these two schemes are hard faults and transient faults respectively. Recently, ECC also became a popular solution to correct hard errors and then further improve the fabrication yield of memories. In general, defects are randomly distributed in memories. To reach high repair rate, sufficient spares are required to repair the faults. If the number of spares is less than expected, the repair would be failed.
In order to cure this drawback, efficient logical to physical address remapping techniques are proposed in this paper, called fault clustering techniques. The goal is to cluster the faulty cells into the same row or the same word, so that we can improve the efficiency of spares and the fabrication yield. To implement the fault clustering techniques, heuristic fault clustering algorithms suitable for built-in implementation are proposed to sequentially remap logical address for each memory bank. The corresponding built-in remapping analysis circuit is then derived. It can be easily integrated into the conventional built-in self-repair (BISR) module. A simulator is developed to evaluate the repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.

致謝 I
摘要 II
Abstract III
目錄 IV
圖目錄 VI
表目錄 IX
第一章 簡介 1
1.1動機及背景 1
1.2組織架構 4
第二章 隨機存取記憶體內建自我測試、診斷和修復技術 5
2.1記憶體架構 5
2.2故障模型 6
2.3測試演算法 8
2.4內建自我測試 10
2.5內建自我診斷及修復 13
第三章 錯誤檢查及修正技術 16
3.1錯誤修正碼 16
3.1.1漢明碼 (Hamming Code) 16
3.1.2修正漢明碼 (Modified Hamming Code) 17
3.1.3蕭氏碼 (Hsiao Code) 17
3.2傳統結合錯誤修正碼與內建自我修復技術之測試與修復流程 19
第四章 內建故障群集技術 22
4.1內建故障群集基本概念 22
4.1.1列群集 (Row Clustering) 技術 24
4.1.2行群集 (Column Clustering) 技術 25
4.1.3混合型群集 (Hybrid Clustering) 技術 27
4.2內建故障群集演算法 28
4.3內建故障群集技術之硬體架構 39
4.4內建故障群集技術之測試與修復流程 43
第五章 實驗結果 46
5.1瑕疵分布與故障型態之設定 46
5.2修復率分析 48
5.3良率分析 53
5.4可靠度分析 56
5.5硬體成本分析 59
5.6超大型積體電路實現 64
第六章 結論與未來展望 66
6.1結論 66
6.2未來展望 66
參考文獻 67

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