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研究生:林祐萱
研究生(外文):Yu-Hsuan Lin
論文名稱:多重閘極場效電晶體之行為模型及低功耗邏輯電路之研究 (含Omega閘極、四閘極及混合多重閘極電晶體)
論文名稱(外文):The Investigation on Behavior Model and Low-Power Logic gate for Multiple-Gate FETs (including Omega-Gate, Quadruple-Gate and Hybrid Multiple-Gate FETs)
指導教授:江德光
指導教授(外文):Te-Kuang Chiang
口試委員:林吉聰陳志方
口試委員(外文):Jyi-Tsong LinJone-Fang Chen
口試日期:2019-07-26
學位類別:碩士
校院名稱:國立高雄大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:英文
論文頁數:233
中文關鍵詞:有效傳導路徑微縮理論短通道效應多閘極金氧半場效電晶體多閘極穿隧式場效電晶體次臨界邏輯電路
外文關鍵詞:Effective-conduction-pathScaling TheoryShort-Channel EffectsMultiple-Gate MOSFETsMultiple-Gate TFETsSubthreshold Logic circuit
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為了因應未來高堆疊密度電路所需微小元件之需求,具良好短通道之控制行為與高堆疊密度之立體元件如三閘極金氧半場效電晶體(Triple-Gate MOSFETs)、四閘極金氧半場效電晶體(Quadruple-Gate MOSFETs) 與Ω閘極金氧半場效電晶體(Omega-Gate MOSFETs),取代了因缺乏短通道控制特性的傳統平面電晶體(Planar Transistor)。近年來,為解決許多元件以及製程的問題,提出了穿隧式場效電晶體(Tunnel Field-Effect transistors),其具有次臨界斜率(Subthreshold Slope, SS)可以突破60mV/dec的限制及關閉漏電流非常低的優點,適合運用在低功耗電路之應用。過去數十年來,雖然有關於多閘極金氧半場效電晶體與雙閘極穿隧式場效電晶體之次臨界行為的研究,但對於多閘極金氧半場效電晶體(Multiple-Gate MOSFETs)元件在電性參數改變的影響以及穿隧式場效電晶體之3-D元件分析相關的研究仍相當欠缺。所以本論文針對在元件上改變其元件參數並將元件套用在邏輯電路上,以我們之前所推導出來的次臨界電流公式,可以導出邏輯電路模型並探討其邏輯電路的特性變化,將來可以被有效應用於各種的記憶體電路中。
本論文乃基於帕森方程式之半二/三維解、微縮理論和周長權值比,成功地推導出多閘極場效電晶體具氧化層基體絕緣結構和次臨界邏輯之行為模型,此模型不僅顯示出元件的電位分佈(Potential Distribution)、次臨界斜率、汲極導致能障降低(DIBL)、汲極導致能障變薄(DIBT)、臨界電壓衰減(Threshold Voltage Degradation, Vth roll-off)和汲極電流(Drain Current, ID)等,還有雜訊邊界(Noise Margin, NM)、邏輯擺幅(Logic Swing, LS)和平均直流功率消耗(Average DC Power Consumption, PDC)。此模型之演算結果與模擬數據相當接近,足以提供基本元件設計之導向。

To meet the demand for small devices required for future high-stack density circuits, three-dimensional devices with good short-channel control behavior and high stacking density, such as Triple-Gate MOSFETs, Quadruple-gate MOSFETs and Omega-Gate MOSFETs replace traditional planar transistors that scarce short-channel control characteristics. In recent years, in order to solve many devices and process problems, a Tunnel Field-Effect transistor has been proposed, which has a Subthreshold Slope (SS) that can exceed the limit of 60mV / dec and the small off-state current; therefore, it's suitable for applications in low power circuits. In the past few decades, although there have been studies on the subthreshold behavior of Multiple-Gate MOSFETs and Double-gate TFET, it is still quite lacking the research on the influence of devices with the variety of electrical parameters for Multiple-Gate MOSFETs and the analysis of 3-D device of Multiple-Gate tunnel field-effect transistors (TFETs). In this thesis, we will focus on changing the device parameters to analysis the behavior that from device to its application in the logic circuit.
Based on the quasi-2-D/3-D solution of the Poisson’s equation, scaling theory and perimeter-weighted-ratio, this thesis successfully propose the behavior model for Multiple-Gate FETs. This model not only shows the potential distribution, the subthreshold slope, drain-induced barrier lowering (DIBL), drain-induced barrier thinning (DIBT), threshold voltage roll-off and the drain current but also can be used to analyze the DC behavior of the logic circuit, such as noise margin, logic swing and average DC power consumption. All of the models provide a basic guidance to design the MG devices and the logic circuits.

摘要
Abstract
Acknowledgements
Contents
List of Figures
List of Tables
Chapter 1 Introduction
1.1 Motivation of the thesis
Chapter 2 A New Short-Channel Model with Effective-Conducting-Path Included for Omega-Gate MOSFETs
2.1 Introduction
2.2 Scaling Length Equation and Quasi-3-D Subthreshold Potential Model
2.3 Scaling Factor and Design Space
2.4 Discussions
Chapter 3 A New Analytical Model with/without source/drain Depletion region for Quadruple-Gate TFET (QG TFET)
3.1 Introduction
3.2 A New Analytical Model without source/drain Depletion Region for Quadruple-Gate TFET (QG TFET)
3.2.1 Surface Potential Model
3.2.2 Electrical Field Model
3.2.3 Minimum Tunnel Path Model in source/channel region and channel/drain region
3.2.4 On/Off-state Drain Current Model
3.2.5 Threshold Voltage Model
3.2.6 Average Subthreshold Slope Model
3.2.7 Scaling Factor and Allowable Minimum Channel Length
3.2.8 Results and discussions
3.3 A New Analytical Model with source/drain Depletion region for Quadruple-Gate TFET (QGTFET)
3.3.1 Surface Potential Model
3.3.1.1 Quasi-1-D Surface Potential Model in the source region
3.3.1.2 Quasi-1-D Surface Potential Model in the drain region
3.3.1.3 Quasi-3-D Surface Potential Model in the channel region for Quadruple-gate TFET
3.3.2 Electrical Field Model
3.3.3 Minimum Tunnel Path Model in source/channel region and channel/drain region
3.3.4 On/Off-state Drain Current Model
3.3.5 Threshold Voltage Model
3.3.6 Subthreshold Slope Model
3.3.7 Scaling Factor and Allowable Minimum Channel Length
3.3.8 Results and discussions
3.4 Comparison and Conclusions
Chapter 4 A New Analytical Model with/without source/drain Depletion region for Hybrid Multiple-Gate TFETs (QG+DG TFETs)
4.1 Introduction
4.2 A New Analytical Model without source/drain Depletion Region for Hybrid Multiple-Gate TFETs (QG+DG TFETs)
4.2.1 Surface Potential Model
4.2.1.1 Quasi-3-D Surface Potential Model in the channel region for Quadruple-gate TFET
4.2.1.2 Quasi-2-D Surface Potential Model in the channel region for Double-gate TFET
4.2.2 Electrical Field Model
4.2.3 Minimum Tunnel Path Model in source/channel region and channel/drain region
4.2.4 On/Off-state Drain Current Model
4.2.5 Threshold Voltage Model
4.2.6 Subthreshold Slope Model
4.2.7 Scaling Factor and Allowable Minimum Channel Length
4.2.8 Results and discussions
4.3 A New Analytical Model with source/drain Depletion region for Hybrid Multiple-Gate TFETs (QG+DG TFETs)
4.3.1 Surface Potential Model
4.3.1.1 Quasi-1-D Surface Potential Model in the source region
4.3.1.2 Quasi-1-D Surface Potential Model in the drain region
4.3.1.3 Quasi-2-D Surface Potential Model in the channel region for Quadruple-gate TFET
4.3.1.4 Quasi-2-D Surface Potential Model in the channel region for Double-gate TFET
4.3.2 Electrical Field Model
4.3.3 Minimum Tunnel Path Model in source/channel region and channel/drain region
4.3.4 On/Off-state Drain Current Model
4.3.5 Threshold Voltage Model
4.3.6 Subthreshold Slope Model
4.3.7 Scaling Factor and Allowable Minimum Channel Length
4.3.8 Results and discussions
4.4 Comparison and Conclusions
Chapter 5 An Analytical DC Behavior Model for Junction-Based Omega-Gate MOSFETs with/without Localized Trapped Charges Working on Subthreshold Logic gate
5.1 Introduction
5.2 An Analytical DC Behavior Model for Junction-Based Omega-Gate MOSFETs without Localized Trapped Charges Working on Subthreshold Logic gate
5.2.1 Subthreshold Current Model
5.2.2 Equivalent Circuit Model
5.2.3 Noise Margin Model
5.2.4 Logic Swing Model
5.2.5 Average DC Power Consumption Model
5.2.6 Results and Discussions
5.3 An Analytical DC Behavior Model for Junction-Based Omega-Gate MOSFETs with Localized Trapped Charges Working on Subthreshold Logic gate
5.3.1 Subthreshold Current Model
5.3.2 Equivalent Circuit Model
5.3.3 Noise Margin Model
5.3.4 Logic Swing Model
5.3.5 Average DC Power Consumption Model
5.3.6 Results and Discussions
Chapter 6 Conclusions and Future Works
6.1 Conclusions
6.2 Future Works
References
Publication List
VITA


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