[1]H. Danneels, K. Coddens, and G. Gielen, “A Fully-Digital, 0.3V, 270 nW Capacitive Sensor Interface Without External References,” IEEE Proceedings of the ESSCIRC (ESSCIRC), pp. 287-290, Sep. 2011.
[2][20] S. Y. Fan, M. K. Law, and P. I. Mak, “A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout,” IEEE International Symposium on Integrated Circuits (ISIC), pp. 399-391, Dec. 2014.
[3]A. Savaliya, and B. Mishra, “A 0.3V, 12nW, 47fJ/conv, Fully Digital Capacitive Sensor Interface in 0.18μm CMOS,” IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), pp. 1-6, Jan, 2015.
[4]W. B. Yang, S. J. Xie and I. T. Chuo, “A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS,” The 27th International Technical Conference on Circuit/Systems, Computers and Communications (ITC-CSCC), 15-18, Jul, 2012.
[5]W. B. Yang, C. H. Wang, I. T. Chuo and H. H. Hsu, “A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow-Power Application,” IEEE International Symposium on Intelligent Signal Processing and Communication Systems, pp. 604-608, Nov, 2012.
[6]L. Y. Chiou, C. R. Huang, C. C. Cheng, and Y. L. Tsai, “A 300mV Sub-1pJ Differential 6T Sub-threshold SRAM with Low Energy and Variability Resilient Local Assist Circuit,” IEEE International Symposium on Next-Generation Electronics (ISNE), pp. 337-340, Feb, 2013.
[7]L. Liu, K. Ishikawa, and T. Kuroda, “A 720μW 873MHz-1.008GHz Injection-Locked Frequency Multiplier with 0.3V Supply Voltage in 90nm CMOS,” IEEE Symposium on VLSI Circuits (VLSIC), pp. C140-C141, Jun, 2013.
[8]M. Mendizabel, and C. Chen, “A Low Power Demodulator Using Subthreshold Design,” IEEE Asia-Pacific Conference on Antennas and Propagation (APCAP), pp. 1190-1193, Jul, 2014.
[9]C. E. Hsieh, and S. I. Liu, “A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 325-328, Nov, 2014.
[10]W. Zhao, A. B. Alvarez, and Y. Ha, “A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter with Wide Conversion Range,” IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-5, Feb, 2015.
[11]C. K. Chava and J. S. Martinez, “A Frequency Compensation Scheme for LDO Voltage Regulators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 6, pp. 1041-1050, Jun. 2004.
[12]曾南雄, “無外部電容的CMOS低壓差線性穩壓器, ”國立交通大學電機學院IC設計產業研發碩士班碩士論文, Jan. 2007.[13]S. Lu, W. Huang and S. Liu, “A Fast-Recovery Low Dropout Linear Regulator for Any-Type Output Capacitors,” 2005 IEEE Asian Solid-State Circuits Conference, Hsinchu, pp. 497-500, 2005.
[14]Ka Nang Leung and P. K. T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” in IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003.
[15]C. K. Chava and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 6, pp. 1041-1050, June 2004.
[16]Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P. Chen, K. Watanabe, M. Takamiya and T. Sakurai, “0.5-V Input Digital Low-Dropout Regulator LDO with 98.7% Current Efficiency and 2.7-μA Quiescent Current in 65 nm CMOS,” IEICE Transactions, vol. E94-C, no. 6, pp. 938-944, Jun. 2011.
[17]Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U and Rui P. Martins, “A Fully Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation,” IEEE Transactions on Circuits and Systems II, pp, 683-687, July. 2016.
[18]W. B. Yang, Y. Y. Lin, Y. L. Lo , “Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input ,” Circuits, Systems, and Signal Processing(CSSP), vol. 36, pp 5041-5061, Dec. 2017
[19]J. Liu and Nima Maghari, “A Fully-Synthesizable 0.6V Digital LDO with Dual-Loop Control using Digital Standard Cells,” 2016 14th IEEE international New Circuits and Systems Conference (NEWCAS), Oct. 2016.
[20]Y. H. Lee, S. Y. Peng, C. C. Chiu, A. C. H. Wu, K. H. Chen, Y. H. Lin, S. W. Wang, T. Y. Tsai, C. C. Huang and C. C. Lee, “A Low Quiescent Current Asynchronous Digital-LDO with PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 1018-1030, Apr. 2013.
[21]Fan Yang and Philip K. T. Mok, “A Nanosecond-Transient Fine-Grained Digital LDO with Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control,” IEEE Journal of Solid-State Circuits, vol. 52, pp.1-12, Jun. 2017.
[22] I. E. Sutherland,“Micropipelines”, Communications of the ACM, vol. 32, no. 6, pp. 720–738, 1989.
[23] C. H. van Berkel,“Beware the isochronic fork”, Report UR 003/91, Philips Research Laboratories, 1991.
[24] V. B. Marakhovsky,“ Logic design of asynchronous circuits”, Slides on the course. CS&SE Department, SPbPU.
[25]W. Yang, Y. Lin and Y. Lo, “Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in 90nm CMOS process,” 2014 International Conference on Information Science, Electronics and Electrical Engineering, Sapporo, pp. 1653-1656, 2014.
[26]Y. Huang, Y. Lu, F. Maloberti and R. P. Martins, “A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning,”2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
[27]K. Woo, T. Kim, S. Hwang, M. Kim and B. Yang, “A fast-transient digital LDO using a double edge-triggered comparator with a completion signal,” 2018 International Conference on Electronics, Information, and Communication (ICEIC), Honolulu, HI, pp. 1-4, 2018.
[28]Ming-Dou Ker, Tung-Yang Chen and Chung-Yu Wu, “New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area,” Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, pp. 103-108, 1997.
[29]S. B. Nasir, Y. Lee and A. Raychowdhury, “Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators,” Fifteenth International Symposium on Quality Electronic Design, Santa Clara, CA, pp. 68-75, 2014.