臺灣博碩士論文加值系統

可攜式電子裝置需要由電池提供能量給裝置上的電路，而不同電路所需要的規格也不盡相同，因此需要電源管理電路進行能量的分配，其中數位控制低壓降穩壓器(DLDO)以能操作在低電壓下的優勢，而成為熱門的研究主題，由於應用在數位電路中，代表其負載電流會有劇烈變動的特性，因此傳統DLDO的暫態響應能力已無法提供當前的需求。
本論文提出一個有別於傳統DLDO的新架構，利用輸出電壓與參考電壓的誤差電壓轉換為相位差來控制Power MOS，進而達到穩壓的效果，預期可以加速DLDO於暫態響應的能力，本論文所提出之基於脈波寬度調變之快速數位控制低壓降穩壓器，以Matlab Simulink建立模型並分析且使用聯電40nm製成完成晶片。

關鍵字：電源管理晶片、數位控制低壓降穩壓器、多相位壓控振盪器

Portable electronic devices need to be powered by batteries to the circuits on the device, and different modules require different specifications. One of the advantages of digitally low-dropout regulator is it can operate at low voltages. Using digital logic circuits as DLDO’s output loading means the load current will have the unique characteristic of large and rapid change. Conventional DLDO’s transient response ability has failed to meet modern digital circuits’ load current demand.
This paper proposes a DLDO with new architecture, which converting the error voltage of the output voltage and the reference voltage into a phase difference, and use phase difference to control Power MOS to regulate voltage. We expect to achieve faster transient response ability. The proposed DLDO design uses Matlab Simulink to construct behavior model, through analysis and simulation, finally fabricated on a UMC 40nm CMOS process.

Key words: power management IC, digital low-dropout regulator, multi-phase voltage-controlled oscillator  

目錄
致謝詞 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章 緒論 1
1.1 研究動機與背景 1
1.2 論文架構 2
第二章 數位低壓降穩壓器基本原理與架構分析 3
2.1 數位低壓降穩壓器 3
2.2 近年數位低壓降轉換器論文研究分析 4
2.2.1 Comparator based [2] [3] [4] [5] [6] [7] [8] 4
2.2.2 ADC based[9] 5
2.2.3 V2T/F based [10] [11] [12] 7
2.3 結論 8
第三章 基於脈波寬度調變之快速數位控制低壓降穩壓器設計 9
3.1 設計概念與電路架構 9
3.1.1 整體架構說明 9
3.1.2 區塊一:提供快速穩壓功能 10
3.1.3 區塊二:提供精準穩壓功能 14
3.2 理論分析 15
3.2.1 當Vref > Vout 15
3.2.2 當Vref < Vout 17
3.2.3 當Vref ≈ Vout 18
3.2.4 分析結論 18
3.2.5 若VCO的起始電壓錯誤，則會不會造成系統錯誤? 19
3.2.6 若VDD發生變化，對於系統會造成什麼影響? 19
3.3 Matlab Modeling之設計與模擬 20
3.3.1 MPVCO Modeling 21
3.3.2 模擬結果 22
3.4 電路實現與模擬結果 23
3.4.1 多相位壓控振盪器[13] 23
3.4.2 邊緣觸發之SR閂鎖器[14] 25
3.4.3 動態比較器 26
3.4.4 晶片佈局 27
3.4.5 模擬結果 27
3.4.6 HSPICE Model與Matlab Model之差異 28
第四章 晶片量測 29
4.1 晶片量測考量 29
4.1.1 量測環境 29
4.1.2 電路板設計 29
4.2 晶片量測結果 30
4.2.1 量測結果 30
4.2.2 效能比較 33
第五章 結論與未來規劃 34
5.1 結論 34
5.2 未來規劃 35
參考文獻 35

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