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研究生:張哲瑋
研究生(外文):CHANG, ZHE-WEI
論文名稱:變異容忍之多位元時序偵測電路設計與應用
論文名稱(外文):Design and Application of Multi-Bit TD-EDL for Variation-Resilient Circuits
指導教授:王進賢
指導教授(外文):WANG, JINN-SHYAN
口試委員:黃俊銘王進賢葉經緯林泰吉
口試委員(外文):HUANG, CHUN-MINGWANG, JINN-SHYANYEH, CHING-WEILIN, TAY-JYI
口試日期:2020-07-29
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:29
中文關鍵詞:多位元時序儲存元件設計變異容忍時序錯誤偵測
外文關鍵詞:Multi-bit Flip-Flop designVariation toleranceTiming-error detection
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  • 被引用被引用:0
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傳統設計為提升良率,通常需要保證電路在最差的操作條件下(worst corner)仍可照常運作,隨著設計晶片複雜度的提升,減少功率消耗已成為現今科技所重視的議題,因此multi-bit flip-flop被提出並且能有效降低功率消耗。然而,隨著製程的演進,變異變得十分嚴重,有別於傳統worst case design的抗變異電路設計相繼被提出,並且能真正改善傳統過份保守的電路設計。抗變異電路設計搭配著具有偵錯能力的時序儲存元件,因此,為了更進一步提升電路效能以及減少功率校耗,本論文提出多位元時序偵測儲存元件設計。我們分別將Error-detecting Register (EDR)以及本實驗室所提出的抗變異電路TRTB中的Adaptive Register (AR)結合multi-bit技術,於typical case條件下,4-bit EDR相較single-bit EDR節省12%功率消耗;2-bit AR相較single-bit AR節省10%功率消耗。
In order to improve the yield rate of traditional design, it is usually necessary to ensure that the circuit can still operate as usual under the worst operating conditions (worst corner). As the complexity of the design chip increasing, reducing power consumption has become an important issue in today's technology. Therefore, multi -bit flip-flop was proposed and can effectively reduce power consumption. However, with the evolution of the process, the variation has become very serious. and variation tolerance circuit designs that are different from the traditional worst case design have been proposed, and can truly improve the traditional over-conservative circuit design. The variation tolerance circuit design is equipped with timing storage components with error detection capabilities. Therefore, in order to further improve circuit performance and reduce power consumption, this paper proposes a multi-bit timing-detecting storage component design. We combine multi-bit technology with Error-detecting Register (EDR) and Adaptive Register (AR) of TRTB proposed by our laboratory. In typical cases, 4-bit EDR reduce 12% power consumption compared with single-bit EDR. 2-bit AR reduce 10% power consumption compared with single-bit AR.
摘要
Abstract
目錄
圖目錄
表目錄
第一章 序論
第二章 Review Previous Multi-Bit Flip-Flop Designs
2.1 變異介紹
2.2 Design of Multi-Bit Flip-Flops
第三章 Design of Multi-Bit Error-Detecting Registers
3.1 TED
3.2 EDR電路介紹及其設計考量
3.3 Design of Multi-Bit EDRs
第四章 Timing Relaxation and Timing Borrow介紹與Multi-Bit Adaptive Register Design
4.1 Timing Relaxation and Timing Borrow
4.2 Adaptive Register電路架構及優化
4.3 Design of Multi-Bit Adaptive Registers
4.4 Multi-Bit AR應用與模擬結果
第五章 總結
參考文獻

[1]Jinn-Shyan Wang and Shih-Nung Wei, "Comparative analysis of flip-flops in sub- and near-threshold operations," 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, 2014, pp. 1-2.
[2]M.P.H. Lin, C.C. Hsu, and Y.T. Chang, “Post-placement power optimization with multi-bit flip-flops,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 12, pp.1870–1882, 2011.
[3]C. C. Hsu, Y.C. Chen and M.P.H. Lin, “In-Placement Clock-Tree Aware Multi-Bit Flip-Flop Generation for Power Optimization,” Proc. of IEEE International Conference on Computer-Aided Design, 2013.
[4]S. Das et al., “A self-tuning DVS processor using delay-error detection and correction,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792-804, Apr. 2006.
[5]K. Bowman et al., “Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 49-63, Jan. 2009.
[6]S. Kim et al., “Razor-Lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf., 2013, pp. 264 - 265.
[7]Y. Zhang et al., “iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor,” in Proc. IEEE Int. Solid-State Circuits Conf., 2016, pp. 160 - 161.
[8]Y. Zhang et al., “iRazor: current-based error detection and correction scheme for PVT variation in 40-nm ARM Cortex-R4 processor,” IEEE J. Solid-State Circuits, vol. 53, no. 2, pp. 619-631, Feb. 2018.
[9]Jinn-Shyan Wang and Shih-Nung Wei, “Process/Voltage/Temperature-variation-aware design and comparative study of transition-detector-based error-detecting latches for timing-error-resilient pipelined systems,” IEEE Trans. Very Large Scale Integration (VLSI) System, vol. 25, no. 10, pp.2893-2906, Oct. 2017.
[10]C. Liu, Z. Chang, S. Wei, J. Wang and T. Lin, "A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs," 2018 31st IEEE International System-on-Chip Conference (SOCC), Arlington, VA, 2018, pp. 1-6.
[11]李崑生 (2020)。基於放寬時序限制且不需系統暫停及電壓調整之抗變異電路設計。國立中正大學電機工程研究所,嘉義縣。

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