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研究生:黃中勳
研究生(外文):HUANG, CHUNG-HSUN
論文名稱:應用於低頻系統之低功率OTA-C負群組延遲電路設計
論文名稱(外文):The Design of Low Power OTA-C Negative Group Delay Circuit Used in Low Frequency Systems
指導教授:林國珍
指導教授(外文):LIN, KUO-JEN
口試委員:謝曜式莊添民林國珍
口試委員(外文):SHIEH, YAW-SHIHCHUANG, TIEN MINLIN, KUO-JEN
口試日期:2020-07-14
學位類別:碩士
校院名稱:中華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:78
中文關鍵詞:轉導式運算放大器低通濾波器負群組延遲進階的負群組延遲
外文關鍵詞:Transconductance Operational AmplifiersLow-pass FiltersNegative Group DelayAdvanced Negative Group Delay
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本文採用0.18µm CMOS技術進行模擬,使用兩種不同的轉導式運算放大器來設計低通濾波器和負群組延遲。此二電路的提供0.6V之電壓,MOS皆在次臨界區運作,使用差動輸入,單端輸出架構,米勒補償電容大小為100fF。當我們將此二電路接做低通濾波器時,假設截止頻率皆在50Hz。輸入訊號頻率為50Hz,訊號大小為80mVPP的正弦波,會得到輸入訊號大約0.707倍的輸出,並且和輸入訊號相比有36°的延遲。如果在低通濾波器的輸出串接一個負群組延遲之電路,負群組延遲的輸出會是沒有延遲的訊號。若單獨對負群組延遲和進階的負群組延遲進行模擬,輸入心電圖中的QRS波,會得到近似於QRS波且和輸入訊號相比是提前的輸出波型。此二電路不同的地方為MOS之寬長比,可承受之輸入訊號大小分別為80mVPP和160mVPP,當接做低通濾波器時功耗分別為1.9nW和3nW。若加上負群組延遲之電路,功耗分別為5.7nW和9nW。
This article uses 0.18µm CMOS technology for simulation and uses two different transconductance operational amplifiers to design low-pass filters and negative group delay. The two circuits operate with 0.6V voltage supply. MOS operates in the subthreshold region, using differential input, single-ended output architecture, and Miller compensation capacitor size of 100fF. When we connect these two circuits as a low-pass filter, it is assumed that the cut-off frequency is both at 50 Hz. The input signal frequency is 50Hz and the signal size is a sine wave of 80mVPP. The output is about 0.707 times the input signal, and there is a 36° delay compared with the input signal. If a negative group delay circuit is connected in series to the output of the low-pass filter, the negative group delay output will be a signal without delay. If the negative group delay and the advanced negative group delay are simulated separately, and the QRS wave in the ECG is input, an output waveform similar to the QRS wave and earlier than the input signal will be obtained. The difference between these two circuits is the width-to-length ratio of the MOS. The input signal sizes that can be tolerated are 80mVPP and 160mVPP respectively, and the power consumption when connected as a low-pass filter is 1.9nW and 3nW, respectively. If the circuit with negative group delay is added, the power consumption is 5.7nW and 9nW respectively.
摘要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章緒論 1
1.1研究背景 1
1.2研究動機與目的 1
1.3論文概要 1
第二章轉導式運算放大器 2
2.1簡介 2
2.2一階轉導式運算放大器 2
2.3二階轉導式運算放大器 3
2.4增強型之二階轉導式運算放大器 5
2.5二種轉導式運算放大器之差異 6
2.6偏壓電路 6
第三章利用轉導式運算放大器實現之低通濾波器 8
3.1低通濾波器 8
3.2轉導式運算放大器等效電阻 9
3.3利用轉導式運算放大器實現之低通濾波器 10
3.4調整低通濾波器的截止頻率 11
第四章利用轉導式運算放大器實現之負群組延遲 20
4.1群組延遲 20
4.2負群組延遲 20
4.3利用轉導式運算放大器實現之負群組延遲 22
4.4負群組延遲之模擬 22
4.5不同截止頻率的低通濾波器和負群組延遲之模擬 25
4.6進階的負群組延遲之模擬 34
4.7兩種負群組延遲之模擬與比較 37
第五章轉導式運算放大器之佈局與模擬 40
5.1轉導式運算放大器之佈局 40
5.2低通濾波器模擬結果 43
5.3負群組延遲模擬結果 43
5.4改良佈局模擬 44
5.5改良佈局後低通濾波器模擬 45
5.6改良佈局後負群組延遲模擬 49
5.7改良佈局後兩種負群組延遲之模擬與比較 54
第六章模擬結果比較 57
6.1簡介 57
6.2共模拒斥比 57
6.3電源拒斥比 57
6.4轉導值 57
6.5功率 58
6.6各個模擬結果比較 58
第七章結論 62
參考文獻 63

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