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研究生:戴維頡
研究生(外文):Wei-Chieh Tai
論文名稱:應用於神經紀錄系統晶片之前端類比電路研究
論文名稱(外文):Analog Front-End Research Applied in Implantable Neural Recording System-On-a-Chip
指導教授:鍾文耀鍾文耀引用關係
指導教授(外文):Wen-Yaw Chung
學位類別:碩士
校院名稱:中原大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:104
中文關鍵詞:循續漸近式類比數位轉換器神經訊號放大器電容比例式分離電容陣列式 數位轉換器
外文關鍵詞:successive approximation register analog-to-digital converterneural signal amplifiercapacitance proportionaldiscrete capacitor array digital converter
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在神經科學中,神經紀錄系統的開發對於腦科學與生物醫療之研究是非常重大的突破。神經紀錄系統主要是為了探測各種神經疾病與輔助神經科學研究,例如:癲癇、帕金森氏症、中風與人工視網膜等。利用神經紀錄系統可以偵測到微小的神經生醫訊號,並且將其紀錄以讓人們進行分析與研究。由於近年來,隨著半導體製程技術的進步,電子設備愈來愈趨於微小化,這也因此促進了可攜帶式與可植入式產品的開發。這種技術之革新,使神經紀錄系統之設計亦從原本的非開顱式裝置轉變成可植入式之裝置,而這也讓可植入式神經紀錄系統晶片變成醫學工程研究的重要議題之一。因為此可植入式之晶片是植入於人體中,所以在進行設計時,需要考量溫度、低功耗與低雜訊之效應。而為了達至此目的,此晶片通常使用前端之類比電路以抑制雜訊,並且使用類比數位轉換器將處理完之訊號轉換成數位碼,再通過無線傳輸電路將此訊號傳至資料庫進行儲存與分析。此可植入式神經紀錄系統晶片之前端電路是由神經訊號放大器與類比數位轉換器
所構成,而這就是本篇論文所研究之核心。
神經訊號放大器主要是利用低雜訊放大器來實現,而低雜訊放大器是為了處理經由片微電極所讀出之神經訊號,並進行放大與濾波。在本研究中,採用電容回授之方式來設計此低雜訊放大器,電容回授之方式是使用回授電容與電阻作為高通濾波器,再利用再循環折疊疊接放大器形成低通濾波器來達到帶通之特性。類比數位轉換器是將神經類比訊號取樣並轉換成數位碼以利於後續的訊號處理之核心電路。在類比數位轉換器研究中,則採用循續漸近式類比數位轉換器架構以達到低功耗之目的,並設計電容比例式、分離電容陣列式之數位類比轉換器與寬擺幅之動態比較器以應用於此 ADC。
本論文提出之電路皆採用聯華電子公司 0.18um 1P6M 的混合訊 CMOS 製程所設計與布局。在此次設計中,低雜訊放大器之增益可達至54.1 dB,頻帶範圍約為1 Hz~10k Hz。而類比數位轉換器則可達至6 位元的精準度、5M Hz 速度與400k Hz 之取樣率。
In neuroscience, the development of neural recording systems has been a breakthrough in the study of brain science and biomedicine. The neural recording systems are normally used to detect various neurological diseases and assisted neuroscience research, such as epilepsy, Parkinson''s disease, stroke, and artificial retina. The neural recording system can detect tiny neuro-medical signals and record them for analysis and research. In recent years, with the advancement of semiconductor process technology, electronic devices have become more and more miniaturized, which has rapidly promoted the development of portable and implantable products. This technological innovation has transformed the design of the neural recording system from the original non-invasive device into the implantable device. As a result, the system-on-chip (SOC) development of an implantable neural recording system plays an important role in medical engineering research. Because the implantable chip is implanted in the human body, some of the crucial factors such as temperature control,
low-power consumption, and low noise effects are required to be more considered while designing. For achieving the above goal, the chip usually uses an analog circuit of the front end to suppress noise, applies an analog-digital converter to convert the processed signal into a digital code, and then transmits the signal to the database for accessing and analyzing through the wireless transmission circuit. Moreover, the front-end circuit of the chip in the implantable neural recording system is composed of a neural signal amplifier and an analog-digital converter, which is the core of this thesis.
The neural signal amplifier is mainly realized by using a low noise amplifier (LNA), and the low noise amplifier is for processing the neural signals of reading out of the patch microelectrode and allowing them to be amplified and filtered. In this study, the low-noise amplifier is designed by the capacitive feedback where the method of the capacitor feedback utilizes the feedback capacitors and resistors as high-pass filters, and then uses a successive approximation register analog-to-digital converter (SAR ADC) to generate a low-pass filter for achieving the feature of the bandpass. The analog-to-digital converter is the core circuit, which samples and converts neural analog signals into digital codes for facilitating the subsequent signal processing. In the research of the analog-to-digital converter, an architecture of the successive approximation register analog-to-digital converter (SAR ADC) is dedicated to achieving low-power consumption, in which a capacitive proportional, discrete capacitor array digital converter and a wide swing dynamic comparator are all well-designed.
The proposed circuit in this thesis is designed and laid out by the UMC''s 0.18um 1P6M hybrid CMOS process. The results of the implemented simulations reveal that the low noise amplifier can achieve a gain of up to 54.1 dB, and a frequency band range of 1 Hz to 10 kHz and the analog-digital converter can perform up to 6-bit accuracy, 5M Hz speed, and 400k Hz sampling rate.
摘要 ........................................................................................................................................ I
Abstract ................................................................................................................................ II
Acknowledgment ................................................................................................................. IV
Table of Contents .................................................................................................................. V
List of Figures ..................................................................................................................... VII
List of Tables ........................................................................................................................ X
Chapter 1. Introduction .......................................................................................................... 1
1.1 Background of Study ................................................................................................... 1
1.2 Neural Recording Technology ..................................................................................... 2
1.2.1 Introduction to Neural Cells and Cell Membrane Potential ................................................ 2
1.2.2 Implantable Neural Recording System ............................................................................... 4
1.3 Objectives and Motivation ........................................................................................... 5
1.3.1 Accurately Detect Neural Signals via Microelectrodes of Neural Cells............................... 5
1.3.2 Construct a Low Noise Amplifier to Handle Noise ............................................................. 6
1.3.3 Exploit SAR ADC Structure to Accurately Sampling Neural Signals ................................... 8
1.3.4 Satisfying the Specifications of Neural Signals and Circuit Design ..................................... 9
1.4 Thesis Organization ................................................................................................... 10
Chapter 2. Review of Related Literature ............................................................................... 11
2.1 Low Noise Amplifier & Psuedo- Resistor .................................................................. 11
2.1.1 Low Noise Amplifier Design ............................................................................................ 11
2.1.2 Application to Psuedo Resistor ........................................................................................ 14
2.2 Digital-to-Analog Converter & Comparator ............................................................... 15
2.2.1 Digital-to-Analog Converter for SAR ADC ...................................................................... 15
2.2.2 Comparators for SAR ADC .............................................................................................. 16
Chapter 3. The Low Noise Amplifier Design via Neural Recording SOC ............................. 18
3.1 Noise Concept ........................................................................................................... 18
3.1.1 Thermal Noise ................................................................................................................. 18
3.1.2 Flicker Noise ................................................................................................................... 20
3.1.3 Shot Noise ....................................................................................................................... 20
3.2 LNA''s noise efficiency factor (NEF) .......................................................................... 21
3.3 The EKV Model for Low-Power IC Design ............................................................... 21
3.4 LNA Amplifier Using Capacitive Feedback Design ................................................... 23
3.4.1. Design Process of the LNA Amplifier .............................................................................. 24
3.4.2. The architecture of the LNA Amplifier............................................................................. 24
3.4.3. The Design for Pseudo Resistor ...................................................................................... 28
Chapter 4. Successive Approximation Register ADC Technology ........................................ 30
4.1 ADC Theory and Performance Metrics ...................................................................... 30
4.1.1 Resolution and Quantization Error .................................................................................. 30
4.1.2 Static Performance .......................................................................................................... 30
4.1.3 Dynamic Performance ..................................................................................................... 32
4.2 The Architecture of SAR ADC .................................................................................. 32
4.2.1 Successive Approximation Algorithm ............................................................................... 33
4.2.2 Charge Redistribution Architecture ................................................................................. 34
4.3 Sample and Hold (S/H) .............................................................................................. 34
4.4. Comparator ............................................................................................................... 36
4.4.1. Performance Metric of Comparator ................................................................................ 37
4.4.2. Comparator architecture ................................................................................................ 37
4.4.3. The performance simulation of Three-Type Dynamic Comparators ................................. 41
4.5. Digital to Analog Converter ...................................................................................... 45
4.5.1. Performance Metrics of a Digital-to-Analog Converter ................................................... 45
4.5.2. The Architecture of Capacitive Digital-to-Analog Converters ......................................... 46
4.6. Successive Approximation Register Control Logic ................................................... 53
4.6.1 How SAR Control Logic Work With its D-type Flip-flop ................................................... 53
4.6.2. The Simulation Result of SAR Control Logic ................................................................... 56
Chapter 5. Simulation and Analysis of Circuit Design .......................................................... 58
5.1. The Implementation of the Low Noise Amplifier (LNA) .......................................... 58
5.1.1 The Simulation Result of the RFC Amplifier ..................................................................... 61
5.1.2 The Simulation Result of the Pseudo Resistor ................................................................... 63
5.1.3 The Simulation Result of the Low Noise Amplifier ............................................................ 65
5.2. The Implementation of Successive Approximation Register ADC ............................ 67
5.2.1 The Simulation Result in fixed Value of SAR ADC ............................................................ 68
5.2.2 The Simulation Result in ramp signal of SAR ADC ........................................................... 70
5.2.3 The Simulation Result in sine wave signal of SAR ADC .................................................... 73
Chapter 6. Conclusions and Future Work ............................................................................. 76
6.1 Conclusions ............................................................................................................... 76
6.2 Future work ............................................................................................................... 76
References ........................................................................................................................... 78
Appendix ............................................................................................................................. 83
Appendix A. Measurement data of the recycling folded cascode amplifier chip (1st
version) .................................................................................................................... 83
Appendix B. Measurement data of the successive approximation register analog-to-digital
(SAR ADC) chip (1st version) ................................................................................... 87
Appendix C. Questions and Recommendations ................................................................ 93
Curriculum Vitae of Author ................................................................................................. 94


List of Figures
Figure 1-1 (a) Distribution diagram of device (b) Invasive device schematic diagram ........ 1
Figure 1-2 Structure diagram of neural cells /neurons .........................................................2
Figure 1-3 A complete cycle diagram of an action potential ................................................ 3
Figure 1-4 Membrane potential change chart of action potential ......................................... 4
Figure 1-5 The schematic diagram of an implantable neural recording system ....................4
Figure 1-6 Schematic diagram of a Utah electrode array ....................................................5
Figure 1-7 Equivalent circuit model of the electrode-tissue interface .................................. 6
Figure 1-8 schematic diagram of a correlated double sample circuit ...................................7
Figure 1-9 Schematic diagram of a chopper stabilization amplifier .....................................7
Figure 1-10 Schematic diagram of an Instrumentation Amplifier ........................................8
Figure 1-11 Comparisons with the resolution and sample rate for ADC ..............................9
Figure 2-1 Schematic diagram of Bio-amplifier as neural amplifier 11
Figure 2-2 Schematic diagram of the analog front-end [1] 12
Figure 2-3 LNA architectures : CFN, MIFN, CAFN, OLN and MCCFN approaches 14
Figure 2-4 Schematic diagram of FCCFN ........................................................................ 14
Figure 2-5 Psuedo-resistors: a diode-connected and sub-threshold biased MOSFET......... 15
Figure 2-6 Charge-redistribution DAC with binary-weighted capacitor array in [10] 15
Figure 2-7 Charge-scaling DAC using a split array in [22] ............................................... 16
Figure 2-8 Schematic diagram of Baker’s comparator in [23] ........................................... 17
Figure 2-9 Schematic diagram of a dynamic latched comparator in [10] ........................... 17
Figure 3-1 Equivalent model of thermal noise in resistor .................................................. 19
Figure 3-2 Equivalent model of thermal noise in MOSEFT .............................................. 19
Figure 3-3 Architecture diagram of the low noise amplifier 25
Figure 3-4 Architecture diagram of a recycling folded Cascode amplifier ......................... 26
Figure 3-5 Architecture diagram of a feedback pseudo resistor 28
Figure 3-6 R/I curve of a feedback pseudo resistor ........................................................... 28
Figure 3-7 R/TEMP curve of a feedback pseudo resistor 29
Figure 4-1 Schematic diagram for differential nonlinearity of ADC 31
Figure 4-2 Schematic diagram for integral nonlinearity Of ADC ...................................... 31
Figure 4-3 Architecture diagram of a SAR ADC device.................................................... 33
Figure 4-4 Operation process of 3-Bit SAR ADC ............................................................. 34
Figure 4-5 Charge redistribution architecture of DAC device 34
Figure 4-6 Basic architecture diagram of a sample-and-hold device ................................. 35
Figure 4-7 Simulation result of a sample-and-hold circuit ................................................ 36
Figure 4-8 Linear plots for sampling rates of 100 kHz, 200 kHz and 400 kHz .................. 36
Figure 4-9 Schematic diagram of a P-type dynamic latch comparator ............................... 38
Figure 4-10 Schematic diagram of dynamic two-stage latched comparator ....................... 40
Figure 4-11 Schematic diagram of a wide-swing dynamic comparator ............................. 41
Figure 4-12 Simulation result of a P-type dynamic latch comparator ................................ 42
Figure 4-13 Simulation result of a dynamic two-stage latch comparator ........................... 43
Figure 4-14 High-level simulation result of a wide-swing dynamic comparator ................ 44
Figure 4-15 Medium-level simulation result of a wide-swing dynamic comparator .......... 44
Figure 4-16 Low-level simulation result of a wide-swing dynamic comparator 45
Figure 4-17 Differential nonlinearity of DAC device ........................................................ 46
Figure 4-18 Architecture diagram of a charge scaling DAC .............................................. 47
Figure 4-19 Structure of a charge scaling DAC by using split array………………………48
Figure 4-20 Schematic diagram of a 2-to-1 multiplexer in DAC device ............................ 48
Figure 4-21 Input digital code of the charge scaling DAC device ..................................... 49
Figure 4-22 Output results of the charge scaling DAC device ........................................... 49
Figure 4-23 Transfer curve of the charge scaling DAC device .......................................... 50
Figure 4-24 DNL simulation of the charge scaling DAC device ....................................... 50
Figure 4-25 INL simulation of the charge scaling DAC device ......................................... 51
Figure 4-26 Output results of the charge scaling DAC device by using split array ............ 51
Figure 4-27 DNL simulation of the charge scaling DAC device using split array .............. 52
Figure 4-28 INL simulation of the charge scaling DAC device using split array ............... 52
Figure 4-29 Architecture diagram of a SAR control logic unit 53
Figure 4-30 Architecture diagram of a D-type flip-flop .................................................... 54
Figure 4-31 Schematic diagram of operation of SAR control logic ................................... 55
Figure 4-32 Schematic diagram of next operation of SAR control logic 55
Figure 4-33 Simulation result of a D-type flip-flop ........................................................... 56
Figure 4-34 Simulation result of shift register .................................................................. 57
Figure 4-35 Simulation result of SAR control logic .......................................................... 57
Figure 5-1 The flow chart of the IC Tape-out.................................................................... 58
Figure 5-2 Complete architectural diagram of the low noise amplifier .............................. 58
Figure 5-3 Layout design of RFC OPA amplifier .............................................................. 59
Figure 5-4 Layout design of LNA amplifier ..................................................................... 60
Figure 5-5 Layout design of Tape-out chip ....................................................................... 60
Figure 5-6 The DC gain of the RFC amplifier pre-sim in five corner cases 61
Figure 5-7 The DC gain of the RFC amplifier post-sim in five corner cases ..................... 62
Figure 5-8 Relationships between resistance and current of pre-simulation ...................... 63
Figure 5-9 Relationships between resistance and temperature of pre-simulation ............... 64
Figure 5-10 Relationships between resistance and current in post-simulation……………64
Figure 5-11 Relationships between resistance and temperature in post-simulation ............ 65
Figure 5-12 Pre-simulation results of the low noise amplifier in five corner cases 65
Figure 5-13 Post-simulation results of the low noise amplifier in five corner cases ........... 66
Figure 5-14 The whole architecture of the SAR ADC for simulation ................................ 67
Figure 5-15 Layout design of SAR ADC .......................................................................... 68
Figure 5-16 Tape-out chip layout of SAR ADC and DAC................................................. 68
Figure 5-17 The input signals and DAC outputs of the SAR ADC .................................... 69
Figure 5-18 Simulation results for the output result of each bit in SAR ADC.................... 69
Figure 5-19 Flow chart of correction and regulation in SAR ADC 70
Figure 5-20 Digital output code of SAR ADC for ramp input signal ................................. 71
Figure 5-21 Real Digital output code of 10 bit for ramp input signal……………………..71
Figure 5-22 DNL results of SAR ADC ............................................................................. 72
Figure 5-23 INL results of SAR ADC............................................................................... 72
Figure 5-24 INL and DNL results of correction and regulation. ........................................ 73
Figure 5-25 Input signal and DAC output of SAR ADC for the sine wave signal .............. 73
Figure 5-26 Digital code of SAR ADC for the sine wave signal ....................................... 74
Figure 5-27 FFT Simulation result of SAR ADC .............................................................. 74

List of Tables
Table 1 Specification sheet for circuit design .................................................................... 10
Table 2 PSD of four operating region in MOSEFT ........................................................... 19
Table 3 Transistor sizes of a RFC amplifier in weak inversion region ............................... 28
Table 4 Transistor sizes of a P-type dynamic latch comparator ......................................... 39
Table 5 Transistor sizes of a dynamic two-stage latch comparator .................................... 40
Table 6 Transistor sizes of a wide-swing dynamic comparator .......................................... 41
Table 7 Performance simulation status of a P-type dynamic latch comparator .................. 42
Table 8 Performance simulation status of a dynamic two-stage latch comparator.............. 43
Table 9 The result of performance simulation for a wide-swing dynamic comparator ....... 45
Table 10 The truth table of a D-type flip-flop device ........................................................ 54
Table 11 The utilized parameters of the capacitive component in LNA ............................. 59
Table 12 The parameter characteristics of the RFC amplifier in the pre-simulation ........... 61
Table 13 The post-simulation parameter characteristics of the RFC amplifier ................... 62
Table 14 The pre-simulation parameter characteristics of LNA ........................................ 66
Table 15 The post-simulation parameter characteristics of LNA ....................................... 66
Table 16 The output and regulated results of SAR ADC ................................................... 70
Table 17 The sheet of parameter characteristics of SAR ADC 75
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