臺灣博碩士論文加值系統

摘要 ........................................................................................................................................ I
Abstract ................................................................................................................................ II
Acknowledgment ................................................................................................................. IV
Table of Contents .................................................................................................................. V
List of Figures ..................................................................................................................... VII
List of Tables ........................................................................................................................ X
Chapter 1. Introduction .......................................................................................................... 1
1.1 Background of Study ................................................................................................... 1
1.2 Neural Recording Technology ..................................................................................... 2
1.2.1 Introduction to Neural Cells and Cell Membrane Potential ................................................ 2
1.2.2 Implantable Neural Recording System ............................................................................... 4
1.3 Objectives and Motivation ........................................................................................... 5
1.3.1 Accurately Detect Neural Signals via Microelectrodes of Neural Cells............................... 5
1.3.2 Construct a Low Noise Amplifier to Handle Noise ............................................................. 6
1.3.3 Exploit SAR ADC Structure to Accurately Sampling Neural Signals ................................... 8
1.3.4 Satisfying the Specifications of Neural Signals and Circuit Design ..................................... 9
1.4 Thesis Organization ................................................................................................... 10
Chapter 2. Review of Related Literature ............................................................................... 11
2.1 Low Noise Amplifier & Psuedo- Resistor .................................................................. 11
2.1.1 Low Noise Amplifier Design ............................................................................................ 11
2.1.2 Application to Psuedo Resistor ........................................................................................ 14
2.2 Digital-to-Analog Converter & Comparator ............................................................... 15
2.2.1 Digital-to-Analog Converter for SAR ADC ...................................................................... 15
2.2.2 Comparators for SAR ADC .............................................................................................. 16
Chapter 3. The Low Noise Amplifier Design via Neural Recording SOC ............................. 18
3.1 Noise Concept ........................................................................................................... 18
3.1.1 Thermal Noise ................................................................................................................. 18
3.1.2 Flicker Noise ................................................................................................................... 20
3.1.3 Shot Noise ....................................................................................................................... 20
3.2 LNA''s noise efficiency factor (NEF) .......................................................................... 21
3.3 The EKV Model for Low-Power IC Design ............................................................... 21
3.4 LNA Amplifier Using Capacitive Feedback Design ................................................... 23
3.4.1. Design Process of the LNA Amplifier .............................................................................. 24
3.4.2. The architecture of the LNA Amplifier............................................................................. 24
3.4.3. The Design for Pseudo Resistor ...................................................................................... 28
Chapter 4. Successive Approximation Register ADC Technology ........................................ 30
4.1 ADC Theory and Performance Metrics ...................................................................... 30
4.1.1 Resolution and Quantization Error .................................................................................. 30
4.1.2 Static Performance .......................................................................................................... 30
4.1.3 Dynamic Performance ..................................................................................................... 32
4.2 The Architecture of SAR ADC .................................................................................. 32
4.2.1 Successive Approximation Algorithm ............................................................................... 33
4.2.2 Charge Redistribution Architecture ................................................................................. 34
4.3 Sample and Hold (S/H) .............................................................................................. 34
4.4. Comparator ............................................................................................................... 36
4.4.1. Performance Metric of Comparator ................................................................................ 37
4.4.2. Comparator architecture ................................................................................................ 37
4.4.3. The performance simulation of Three-Type Dynamic Comparators ................................. 41
4.5. Digital to Analog Converter ...................................................................................... 45
4.5.1. Performance Metrics of a Digital-to-Analog Converter ................................................... 45
4.5.2. The Architecture of Capacitive Digital-to-Analog Converters ......................................... 46
4.6. Successive Approximation Register Control Logic ................................................... 53
4.6.1 How SAR Control Logic Work With its D-type Flip-flop ................................................... 53
4.6.2. The Simulation Result of SAR Control Logic ................................................................... 56
Chapter 5. Simulation and Analysis of Circuit Design .......................................................... 58
5.1. The Implementation of the Low Noise Amplifier (LNA) .......................................... 58
5.1.1 The Simulation Result of the RFC Amplifier ..................................................................... 61
5.1.2 The Simulation Result of the Pseudo Resistor ................................................................... 63
5.1.3 The Simulation Result of the Low Noise Amplifier ............................................................ 65
5.2. The Implementation of Successive Approximation Register ADC ............................ 67
5.2.1 The Simulation Result in fixed Value of SAR ADC ............................................................ 68
5.2.2 The Simulation Result in ramp signal of SAR ADC ........................................................... 70
5.2.3 The Simulation Result in sine wave signal of SAR ADC .................................................... 73
Chapter 6. Conclusions and Future Work ............................................................................. 76
6.1 Conclusions ............................................................................................................... 76
6.2 Future work ............................................................................................................... 76
References ........................................................................................................................... 78
Appendix ............................................................................................................................. 83
Appendix A. Measurement data of the recycling folded cascode amplifier chip (1st
version) .................................................................................................................... 83
Appendix B. Measurement data of the successive approximation register analog-to-digital
(SAR ADC) chip (1st version) ................................................................................... 87
Appendix C. Questions and Recommendations ................................................................ 93
Curriculum Vitae of Author ................................................................................................. 94


List of Figures
Figure 1-1 (a) Distribution diagram of device (b) Invasive device schematic diagram ........ 1
Figure 1-2 Structure diagram of neural cells /neurons .........................................................2
Figure 1-3 A complete cycle diagram of an action potential ................................................ 3
Figure 1-4 Membrane potential change chart of action potential ......................................... 4
Figure 1-5 The schematic diagram of an implantable neural recording system ....................4
Figure 1-6 Schematic diagram of a Utah electrode array ....................................................5
Figure 1-7 Equivalent circuit model of the electrode-tissue interface .................................. 6
Figure 1-8 schematic diagram of a correlated double sample circuit ...................................7
Figure 1-9 Schematic diagram of a chopper stabilization amplifier .....................................7
Figure 1-10 Schematic diagram of an Instrumentation Amplifier ........................................8
Figure 1-11 Comparisons with the resolution and sample rate for ADC ..............................9
Figure 2-1 Schematic diagram of Bio-amplifier as neural amplifier 11
Figure 2-2 Schematic diagram of the analog front-end [1] 12
Figure 2-3 LNA architectures : CFN, MIFN, CAFN, OLN and MCCFN approaches 14
Figure 2-4 Schematic diagram of FCCFN ........................................................................ 14
Figure 2-5 Psuedo-resistors: a diode-connected and sub-threshold biased MOSFET......... 15
Figure 2-6 Charge-redistribution DAC with binary-weighted capacitor array in [10] 15
Figure 2-7 Charge-scaling DAC using a split array in [22] ............................................... 16
Figure 2-8 Schematic diagram of Baker’s comparator in [23] ........................................... 17
Figure 2-9 Schematic diagram of a dynamic latched comparator in [10] ........................... 17
Figure 3-1 Equivalent model of thermal noise in resistor .................................................. 19
Figure 3-2 Equivalent model of thermal noise in MOSEFT .............................................. 19
Figure 3-3 Architecture diagram of the low noise amplifier 25
Figure 3-4 Architecture diagram of a recycling folded Cascode amplifier ......................... 26
Figure 3-5 Architecture diagram of a feedback pseudo resistor 28
Figure 3-6 R/I curve of a feedback pseudo resistor ........................................................... 28
Figure 3-7 R/TEMP curve of a feedback pseudo resistor 29
Figure 4-1 Schematic diagram for differential nonlinearity of ADC 31
Figure 4-2 Schematic diagram for integral nonlinearity Of ADC ...................................... 31
Figure 4-3 Architecture diagram of a SAR ADC device.................................................... 33
Figure 4-4 Operation process of 3-Bit SAR ADC ............................................................. 34
Figure 4-5 Charge redistribution architecture of DAC device 34
Figure 4-6 Basic architecture diagram of a sample-and-hold device ................................. 35
Figure 4-7 Simulation result of a sample-and-hold circuit ................................................ 36
Figure 4-8 Linear plots for sampling rates of 100 kHz, 200 kHz and 400 kHz .................. 36
Figure 4-9 Schematic diagram of a P-type dynamic latch comparator ............................... 38
Figure 4-10 Schematic diagram of dynamic two-stage latched comparator ....................... 40
Figure 4-11 Schematic diagram of a wide-swing dynamic comparator ............................. 41
Figure 4-12 Simulation result of a P-type dynamic latch comparator ................................ 42
Figure 4-13 Simulation result of a dynamic two-stage latch comparator ........................... 43
Figure 4-14 High-level simulation result of a wide-swing dynamic comparator ................ 44
Figure 4-15 Medium-level simulation result of a wide-swing dynamic comparator .......... 44
Figure 4-16 Low-level simulation result of a wide-swing dynamic comparator 45
Figure 4-17 Differential nonlinearity of DAC device ........................................................ 46
Figure 4-18 Architecture diagram of a charge scaling DAC .............................................. 47
Figure 4-19 Structure of a charge scaling DAC by using split array………………………48
Figure 4-20 Schematic diagram of a 2-to-1 multiplexer in DAC device ............................ 48
Figure 4-21 Input digital code of the charge scaling DAC device ..................................... 49
Figure 4-22 Output results of the charge scaling DAC device ........................................... 49
Figure 4-23 Transfer curve of the charge scaling DAC device .......................................... 50
Figure 4-24 DNL simulation of the charge scaling DAC device ....................................... 50
Figure 4-25 INL simulation of the charge scaling DAC device ......................................... 51
Figure 4-26 Output results of the charge scaling DAC device by using split array ............ 51
Figure 4-27 DNL simulation of the charge scaling DAC device using split array .............. 52
Figure 4-28 INL simulation of the charge scaling DAC device using split array ............... 52
Figure 4-29 Architecture diagram of a SAR control logic unit 53
Figure 4-30 Architecture diagram of a D-type flip-flop .................................................... 54
Figure 4-31 Schematic diagram of operation of SAR control logic ................................... 55
Figure 4-32 Schematic diagram of next operation of SAR control logic 55
Figure 4-33 Simulation result of a D-type flip-flop ........................................................... 56
Figure 4-34 Simulation result of shift register .................................................................. 57
Figure 4-35 Simulation result of SAR control logic .......................................................... 57
Figure 5-1 The flow chart of the IC Tape-out.................................................................... 58
Figure 5-2 Complete architectural diagram of the low noise amplifier .............................. 58
Figure 5-3 Layout design of RFC OPA amplifier .............................................................. 59
Figure 5-4 Layout design of LNA amplifier ..................................................................... 60
Figure 5-5 Layout design of Tape-out chip ....................................................................... 60
Figure 5-6 The DC gain of the RFC amplifier pre-sim in five corner cases 61
Figure 5-7 The DC gain of the RFC amplifier post-sim in five corner cases ..................... 62
Figure 5-8 Relationships between resistance and current of pre-simulation ...................... 63
Figure 5-9 Relationships between resistance and temperature of pre-simulation ............... 64
Figure 5-10 Relationships between resistance and current in post-simulation……………64
Figure 5-11 Relationships between resistance and temperature in post-simulation ............ 65
Figure 5-12 Pre-simulation results of the low noise amplifier in five corner cases 65
Figure 5-13 Post-simulation results of the low noise amplifier in five corner cases ........... 66
Figure 5-14 The whole architecture of the SAR ADC for simulation ................................ 67
Figure 5-15 Layout design of SAR ADC .......................................................................... 68
Figure 5-16 Tape-out chip layout of SAR ADC and DAC................................................. 68
Figure 5-17 The input signals and DAC outputs of the SAR ADC .................................... 69
Figure 5-18 Simulation results for the output result of each bit in SAR ADC.................... 69
Figure 5-19 Flow chart of correction and regulation in SAR ADC 70
Figure 5-20 Digital output code of SAR ADC for ramp input signal ................................. 71
Figure 5-21 Real Digital output code of 10 bit for ramp input signal……………………..71
Figure 5-22 DNL results of SAR ADC ............................................................................. 72
Figure 5-23 INL results of SAR ADC............................................................................... 72
Figure 5-24 INL and DNL results of correction and regulation. ........................................ 73
Figure 5-25 Input signal and DAC output of SAR ADC for the sine wave signal .............. 73
Figure 5-26 Digital code of SAR ADC for the sine wave signal ....................................... 74
Figure 5-27 FFT Simulation result of SAR ADC .............................................................. 74

List of Tables
Table 1 Specification sheet for circuit design .................................................................... 10
Table 2 PSD of four operating region in MOSEFT ........................................................... 19
Table 3 Transistor sizes of a RFC amplifier in weak inversion region ............................... 28
Table 4 Transistor sizes of a P-type dynamic latch comparator ......................................... 39
Table 5 Transistor sizes of a dynamic two-stage latch comparator .................................... 40
Table 6 Transistor sizes of a wide-swing dynamic comparator .......................................... 41
Table 7 Performance simulation status of a P-type dynamic latch comparator .................. 42
Table 8 Performance simulation status of a dynamic two-stage latch comparator.............. 43
Table 9 The result of performance simulation for a wide-swing dynamic comparator ....... 45
Table 10 The truth table of a D-type flip-flop device ........................................................ 54
Table 11 The utilized parameters of the capacitive component in LNA ............................. 59
Table 12 The parameter characteristics of the RFC amplifier in the pre-simulation ........... 61
Table 13 The post-simulation parameter characteristics of the RFC amplifier ................... 62
Table 14 The pre-simulation parameter characteristics of LNA ........................................ 66
Table 15 The post-simulation parameter characteristics of LNA ....................................... 66
Table 16 The output and regulated results of SAR ADC ................................................... 70
Table 17 The sheet of parameter characteristics of SAR ADC 75

[1]Abdelhalim, K. (2013). Wireless neural recording and stimulation SOCS for monitoring and treatment of intractable epilepsy (Doctoral dissertation).
[2]Brenna, S., Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., & Lacaita, A. L. (2016). A 64-Channel 965-μW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(6), 528-532.
[3]Molecular Biology of the Neuron R. Wayne Davies and Brian Morris.
[4]Campbell Biology (11th Edition) (English) 11th, Lisa A. Urry (Author), Michael L. Cain (Author), Steven A. Wasserman (Author), Peter V. Minorsky (Author), Jane B. Reece (Author).
[5]Modeling of the sEMG/Force relationship by data analysis of high-resolution sensor networks.
[6]Harrison, R. R., & Charles, C. (2003). A low-power low-noise CMOS amplifier for neural recording applications. IEEE Journal of solid-state circuits, 38(6), 958-965.
[7]Harrison, R. R., Kier, R. J., Chestek, C. A., Gilja, V., Nuyujukian, P., Ryu, S., ... & Shenoy, K. V. (2009). Wireless neural recording with the single low-power integrated circuit. IEEE transactions on neural systems and rehabilitation engineering, 17(4), 322-329.
[8]Ruiz-Amaya, J., Rodriguez-Perez, A., & Delgado-Restituto, M. (2015). A low noise amplifier for neural spike recording interfaces. Sensors, 15(10), 25313-25335.
[9]Abdelhalim, K., MacEachern, L., & Mahmoud, S. (2006, May). A nanowatt ADC for ultra low power applications. In 2006 IEEE International Symposium on Circuits and Systems (pp. 4-pp). IEEE.
[10]Hedayati, R. (2011). A study of Successive Approximation Registers and implementation of an ultra-low-power 10-bit SAR ADC in 65nm CMOS technology.
[11]Chandrakumar, H., & Marković, D. (2018). A 15.2-ENOB 5-kHz BW 4.5-μW Chopped CT ΔΣ-ADC for Artifact-Tolerant Neural Recording Front Ends. IEEE Journal of Solid-State Circuits, 53(12), 3470-3483.
[12]Hirai, Y., Matsuoka, T., Tani, S., Isami, S., Tatsumi, K., Ueda, M., & Kamata, T. (2019). A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning. IEEE Access, 7, 21990-22001.
[13]Wark, H. A. C., Sharma, R., Mathews, K. S., Fernandez, E., Yoo, J., Christensen, B., ... & Tathireddy, P. (2013). A new high-density (25 electrodes/mm2) penetrating microelectrode array for recording and stimulating sub-millimeter neuroanatomical structures. Journal of neural engineering, 10(4), 045003.
[14]A technique for implantation of a 3-dimensional penetrating electrode array in the modiolar nerve of cats and humans.
[15]Luan, S., Liu, Y., Williams, I., & Constandinou, T. G. (2016, October). An event-driven SoC for neural recording. In 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS) (pp. 404-407). IEEE.
[16]Park, S. Y., Cho, J., Lee, K., & Yoon, E. (2018). Dynamic power reduction in scalable neural recording interface using spatiotemporal correlation and temporal sparsity of neural signals. IEEE Journal of Solid-State Circuits, 53(4), 1102-1114.
[17]Valtierra, J. L., Fiorelli, R., Delgado-Restituto, M., & Rodriguez-Vazquez, A. (2019, February). A Sub-µW Reconfigurable Front-End for Invasive Neural Recording. In 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCARIS) (pp. 85-88). IEEE.
[18]Jung, Y., Jeon, H., Lee, T., Seong, H. Y., Park, C., & Je, M. (2018, June). Technical Review: Neural Recording Circuits for Bidirectional Neural Interface. In 2018 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia) (pp. 206-212). IEEE.
[19]Verma, N., & Chandrakasan, A. P. (2007). An ultra-low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes. IEEE Journal of Solid-State Circuits, 42(6), 1196-1205.
[20]Verma, N., Kwong, J., Ramadass, Y. K., Daly, D. C., Sze, V., Ickes, N., & Chandrakasan, A. P. Low Voltage System Design for Highly Energy Constrained Applications.
[21]Kardonik, O. (2013). A study of SAR ADC and implementation of 10-bit asynchronous design.
[22]Kulkarni, M., Shingadi, M., & Kulkarni, G. H. (2014). 6-Bit Charge Scaling DAC and SAR ADC”. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 3(12).
[23]CMOS. Circuit Design, Layout, and Simulation. Third Edition. R. Jacob Baker.
[24]Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design / Christian Enz and Eric Vittoz.
[25]Sub-threshold design for ultra-low-power systems / Alice Wang, Benton H. Calhoun, Anantha P. Chandrakasan.
[26]Enz, C. C., Krummenacher, F., & Vittoz, E. A. (1995). An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog integrated circuits and signal processing, 8(1), 83-114.
[27]Enhancing the performance of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability.
[28]Abdelhalim, K., Kokarovtseva, L., Velazquez, J. L. P., & Genov, R. (2013). 915-MHz FSK/OOK wireless neural recording SoC with 64 mixed-signal FIR filters. IEEE Journal of Solid-State Circuits, 48(10), 2478-2493.
[29]Chandrakasan, A. P., Verma, N., & Daly, D. C. (2008). Ultralow-power electronics for biomedical applications. Annual review of biomedical engineering, 10.
[30]Bautista-Delgado, A. F. (2009). Design of an ultra-low voltage analog front end for an electroencephalography system (Doctoral dissertation, Université Joseph-Fourier-Grenoble I).
[31]Chapin, J. K., & Moxon, K. A. (2000). Neural prostheses for restoration of sensory and motor function. CRC Press.
[32]Dai, Z., Hu, H., Chen, Y., Ye, F., & Ren, J. (2018, August). A 12-Bit ENOB 8MHz BW noise-shaping SAR ADC Using High-Speed Switches. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 392-395). IEEE.
[33]Hunt, R. (2014). Low Voltage CMOS SAR ADC Design.
[34]Jeon, H., Bang, J. S., Jung, Y., Lee, T., Jeon, Y., Koh, S. T., ... & Je, M. (2018, November). A 3.9 μW, 81.3 dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS. In 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) (pp. 91-92). IEEE.
[35]Kim, S. J., Han, S. H., Cha, J. H., Liu, L., Yao, L., Gao, Y., & Je, M. (2019). A Sub- μW/Ch Analog Front-End for ∆-Neural Recording With Spike-Driven Data Compression. IEEE transactions on biomedical circuits and systems, 13(1), 1-14.
[36]Kursu, Olli-Erkki, Micromotion compensation and a neural recording and stimulation system for electrophysiological measurements. University of Oulu Graduate School; the University of Oulu, Faculty of Information Technology and Electrical Engineering, Department of Electrical Engineering; Infotech Oulu Acta Univ. Oul. C 554, 2015.
[37]Li, C., Chan, C. H., Zhu, Y., & Martins, R. P. (2018). Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC. IEEE Transactions on Circuits and Systems I: Regular Papers, (99), 1-12.
[38]Liu, M., van Roermund, A. H., & Harpe, P. (2019). A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver. IEEE Journal of Solid-State Circuits, 54(2), 417-427.
[39]Mao, W., Li, Y., Heng, C. H., & Lian, Y. (2018). A low power 12-bit 1-kS/s SAR ADC for biomedical signal processing. IEEE Transactions on Circuits and Systems I: Regular Papers, (99), 1-12.
[40]Ranjandish, R., & Schmid, A. (2018, November). A 4-channel 5.04 μW 0.325 mm 2 Orthogonal Sampling-Based Parallel Neural Recording System. In 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) (pp. 27-30). IEEE.
[41]Santana, D., Hernandez, H., & Van Noije, W. (2019, February). A 1.8 V 9bit 10MS/s SAR ADC in 0.18 µm CMOS for bioimpedance analysis. In 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCARIS) (pp. 53-56). IEEE.
[42]Shulyzki, R., Abdelhalim, K., Bagheri, A., Salam, M. T., Florez, C. M., Velazquez, J. L. P., & Genov, R. (2015). 320-channel active probe for high-resolution neuromonitoring and responsive neurostimulation. IEEE transactions on biomedical circuits and systems, 9(1), 34-49.
[43]Sooraj, V. S., & Joseph, G. M. (2018, June). Speed & Resolution Enhancement of 12-Bit SAR ADC. In 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS) (pp. 1655-1658). IEEE.
[44]Thakur, A., & Agarwal, A. (2014). Low-Power Architectures and Self-Calibration Techniques of DAC for SAR-ADC implementation. International Journal of Innovative Research in Electrical, Electronics, Instrumentation, and Control Engineering, 2(3).
[45]Tirunelveli Kanthi, S. (2010). Analysis and; design of successive approximation ADC and 3.5 GHz RF transmitter in 90nm CMOS (Doctoral dissertation, Georgia Institute of Technology).
[46]Wirianto, K. (2016). Multi-Domain SystemC Model of a Neural Interface.
[47]Wu, C., & Yuan, J. (2019). A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC. IEEE Journal of Solid-State Circuits.
[48]Zhang, F., Holleman, J., & Otis, B. P. (2012). Design of ultra-low-power biopotential amplifiers for biosignal acquisition applications. IEEE transactions on biomedical circuits and systems, 6(4), 344-355.