第一單元以功率元件為主
功率金氧半場效應電晶體主要用於電力設備的電能變換和電路控制，是進行電能(功率)處理的核心元件，包括電源供應器、通訊設備、汽車電子、工業電子、消費性電子及顯示器等，尤其是汽車電子產業快速發展，使得該元件需求快速增加。對於功率元件而言，兩項最重要的特性是崩潰電壓(breakdown voltage)與特定導通電阻(Ron,sp)，由於這兩個參數是互相影響的，因此要同時擁有高耐壓和低導通電阻相當不易。典型的功率元件功能包括變頻、變壓、變流、功率放大和功率管理，除保證設備正常運行外，功率元件還起到節能的作用，為了降低功率元件的傳導損耗，低導通電阻元件的研究成為各研究者的競爭目標。
在此，我們提出並研究了具有不同磊晶層(EPI)的150V額定電壓溝槽式分離閘極(SGT)功率金氧半場效電晶體(MOSFET)。為了降低150V SGT功率MOSFET的Ron,sp，我們使用多種EPI結構來設計和比較基於相同製造工藝的單層EPI和雙層EPI元件。我們發現，雙層EPI結構的底層EPI可以用來提供崩潰電壓，並且可以透過調整頂層EPI以降低Ron,sp，因此，雙層EPI元件比單層EPI元件具有更大的靈活性以實現更低的Ron,sp。然而，當所需電壓超過100V時，雙層EPI結構的Ron,sp不再滿足我們的預期，因此我們設計並研究了三層EPI結構，以在不犧牲崩潰電壓的情形下降低Ron。我們使用ISE-TCAD模擬軟體透過調整每層EPI的厚度與電阻率來研究150V SGT功率元件。最後，150V三層EPI元件的模擬Ron值，相較於雙層結構，可擁有81.67%的降低；相較於單層結構，則可擁有38.13%的降低。

第二單元以薄膜電晶體為主
複晶矽薄膜電晶體(Poly-Si TFT)目前被廣泛的運用在面板相關產品上，如主動式液晶顯示器(AMLCD)、像素開關以及外圍驅動電路。相較於非晶矽薄膜電晶體，複晶矽薄膜電晶體可提供較高的載子遷移率和較大的驅動電流，對於大尺寸的顯示器而言可展現更快的開關反應時間和較高的電流來驅動畫素。然而，由於在較高汲極電壓操作下，傳統型複晶矽薄膜電晶體在靠近汲極與通道接面端會產生高電場以及玻璃基板因無基極端點易產生寄生BJT正回授效應，且高電場又是造成離子碰撞的主要原因，這導致了許多不理想效應，如漏電流效應、熱載子效應及扭結效應等而限制其使用範圍。
因此，我們利用一個在近汲極端通道周圍空間等電位結構的設計，提出“利用等電位汲極改善扭結效應之雙閘極複晶矽薄膜電晶體設計”來改善不理想效應，在此設計中我們將薄膜電晶體元件應用雙閘極(double gate)、等電位汲極(equipotential drain)以及分離式通道(split channel)的概念設計並配合ISE-TCAD來預估其特性。此新式結構經過我們的模擬分析，由於採用double gate，使得元件增加約兩倍的開電流。而equipotential drain的設計藉由該處等電位的結構，可以使得近汲極處通道內電壓差趨近於零進而降低該處之電場，還可以使電流遠離高電場區域以改善汲極端的離子碰撞。另外，split channel的設計可以使通道中的N+抑制扭結效應之正回授的發生，因而提升元件的崩潰電壓。此結構不同於過去的結構設計，不僅有效改善汲極端電場，緩和元件扭結效應並降低其離子碰撞產生率使其元件的使用耐壓大幅上升，並可以改善元件之漏電流。在光罩數製程成本的設計上與傳統雙閘極結構相同，不需額外昂貴的製程，不但符合了降低光罩製作成本設計的預算，更能符合市場所需之趨勢。

The first part is based on power components.
Power metal-oxide-semiconductor field-effect transistors are mainly used for power conversion and circuit control of power equipment and are the core components for power processing, including power supplies, communication equipment, automotive electronics, industrial electronics, consumer electronics, and displays. In particular, the rapid development of the automotive electronics industry has led to a rapid increase in demand for this component. For power devices, the two most important characteristics are the breakdown voltage and specific on-resistance (Ron,sp). Since these two parameters affect each other, it is difficult that they have both high breakdown voltage and low on-resistance. Typical power device functions include frequency conversion, voltage transformation, current conversion, power amplification, and power management. In addition, to ensure the normal operation of the device, the power device also plays a role in saving energy. In order to reduce the conduction loss of power devices, the research of low on-resistance elements has become a competitive goal for various researchers.
Therefore, a rating voltage of 150 V split-gate trench (SGT) power metal-oxide-semiconductor field-effect transistor (power MOSFET) with different epitaxial layers have been proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 V SGT power MOSFET, we use multiple epitaxies (EPIs) structure to design and compared other single and double EPIs devices based on the same fabrication process. We found the bottom epitaxy (EPI) layer of a double EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double EPIs device has more flexibility to achieve a lower Ron,sp than the single EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double EPIs device is no longer satisfying our expected. A triple EPIs structure was designed and studied to reduce its Ron without sacrificing the breakdown voltage. We used Integrated System Engineering-Technology Computer Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple EPIs device is only 81.67 and 38.13 % of that for the double EPIs and single one structure, respectively.

The second part is based on thin film transistor.
Poly-Si TFTs are currently widely used in panel related products such as active matrix liquid crystal displays (AMLCDs), pixel switches, and peripheral driver circuits. Compared to amorphous silicon thin film transistors, polycrystalline silicon thin film transistors provide higher carrier mobility and larger drive current. Exhibiting faster switching reaction time and higher current to drive the pixels for large size displays. However, due to the higher voltage operation, the conventional polycrystalline silicon thin film transistor generates a high electric field near the junction of the drain and the channel, and the glass substrate is prone to parasitic BJT positive feedback effect due to the no base. High electric field is the main cause of impact ionization, which leads to many non-ideal effects, such as leakage current effect, hot carrier effect, and kink effect, which limits its range of use.
Therefore, we used a design a space equal voltage at channel/drain area in a TFT structure, and proposed “A Double Gate Poly-Si Thin Film Transistor Design by Adding a Equipotential Drain to Reduce Kink Effect” to improve the undesirable effect of thin film transistors. In this design, we applied double gate, equipotential drain, and split channel into thin film transistor component, and combined with ISE-TCAD simulation to predict its characteristics. This new structure had been analyzed by our simulation, due to the design of the double gate structure, the on-current of the device had been increased about two times. The design of the equipotential drain structure can make the voltage difference close to zero and reduce the electric field in the channel near the drain electrode. It could also keep the current away from the high electric field region to reduce the impact ionization. In addition, the design of the split channel allowed the N+ in the channel to suppress the positive feedback of the kink effect, thus increasing the breakdown voltage of the component. This structure is different from the previous structure design, not only effectively reduces the drain electric field, alleviates the kink effect of the device, and reduces the rate of impact ionization. Which greatly increases the breakdown voltage of the device, but also can improve the leakage current of the device. The design cost of the mask number process is as same as the traditional double gate structure, and no extra expensive process is required. It not only conforms the budget for reducing the design cost of the mask, but also conforms the trend required by the market.

誌謝 i
摘要 ii
Abstract v
目錄 viii
圖目錄 x
表目錄 xiv

單元一 溝槽式分離閘極功率金氧半場效電晶體之三層磊晶層設計
第一章 緒論 1
1.1 研究背景 2
1.2 常見之POWER MOSFET簡介 4
1.3 SPLIT-GATE TRENCH POWER MOSFET介紹 6
1.4 POWER MOSFET機制 7
1.5 研究動機 16
第二章 文獻探討 17
2.1 利用氧化物設計提高元件性能 17
2.2 利用改變材料提高元件性能 19
2.3 利用磊晶層設計提高元件性能 20
第三章 元件設計與模擬流程 21
3.1 元件結構 21
3.2 模擬製程步驟 22
第四章 模擬結果與分析 27
4.1 三層磊晶層之SGT POWER MOSFET分析 27
4.2 相同磊晶層厚度之SGT POWER MOSFET分析 30
4.3 150 V額定電壓之SGT POWER MOSFET分析 35
4.4 200 V額定電壓之SGT POWER MOSFET分析 41
第五章 結論 44

單元二 利用等電位汲極改善扭結效應之雙閘極複晶矽薄膜電晶體設計
第一章 緒論 45
1.1 研究背景 46
1.2 薄膜電晶體簡介 48
1.3 複晶矽薄膜電晶體關鍵技術 51
1.4 複晶矽薄膜電晶體之不理想效應及其改善方式 54
1.5 研究動機 61
第二章 文獻探討 62
2.1 利用雙閘極提升元件飽和電流 62
2.2 利用分離式閘極改善扭結效應 64
2.3 利用等電位改善高電場 66
第三章 元件設計與模擬流程 67
3.1 元件結構 67
3.2 模擬製程步驟 69
第四章 模擬結果與分析 72
4.1 電位分析 74
4.2 電場分析 76
4.3 離子碰撞分析 80
4.4 電流分析 82
4.5 漏電流分析 84
4.6 輸出特性曲線分析 88
4.7 頂閘極與等電位汲極間之N+長度分析 89
4.8 等電位汲極長度分析 92
第五章 實驗結果與分析 95
5.1光罩設計 95
5.2 實驗製程步驟 99
5.3 元件之SEM分析 101
第四節 電性參數萃取 104
第五節 量測結果與討論 108
第六章 結論 112

[1] M. S. Adler, D. N. Pattanayak, B. J. Baliga, V. A. K. Temple, and H. R. Chang (1987). Device physics and modeling of integrated power de-vices, Proc. of NASECODE V, 1-18.
[2] B. J. Baliga (1991). An overview of smart power technology, IEEE Trans. Electron Devices, 38 (7), 1568-1575.
[3] B. J. Baliga (1994). Power semiconductor devices for variable fre-quency drives. Proc. of IEEE, 82 (8), 1112-1122.
[4] B. J. Baliga (1996). Trends in power semiconductor devices, IEEE Trans. Electron Devices, 43 (10), 1717-1731.
[5] B. J. Baliga (2001). The future of power semiconductor device tech-nology, Proc. of IEEE, 89 (6), 822-832.
[6] W. Zhang, B. Zhang, M. Qiao, L. Wu, K. Mao, and Z. Li (2014). A novel vertical field plate lateral device with ultralow specific on-resistance, IEEE Trans. Electron Devices, 61 (2), 518-524.
[7] R. K. Williams, M. N. Darwish, R. A. Blanchard, R. Siemieniec, P. Rutter, and Y. Kawaguchi (2017). The trench power MOSFET: part I—history, technology, and prospects, IEEE Trans. Electron Devices, 64 (3), 674-691.
[8] R. K. Williams, M. N. Darwish, R. A. Blanchard, R. Siemieniec, P. Rutter, and Y. Kawaguchi (2017). The trench power MOSFET—part II: application specific VDMOS, LDMOS, packaging, and reliability, IEEE Trans. Electron Devices, 64 (3), 692-712.
[9] W. Zhang, L. Ye, D. Fang, M. Qizo, K. Xizo, B. He, Z. Li, and B. Zhang (2019). Model and experiments of small-size vertical devices with field plate, IEEE Trans. Electron Devices, 66 (3), 1416-1421.
[10] L. Chen, O. J. Guy, M. R. Jennings, P. Igic, S. P. Wilks, and P. A. Mawby (2005). Study of 4H-SiC trench MOSFET structures, Solid-State Electron, 49 (7), 1081-1085.
[11] J. W. Palmour, L. Cheng, V. Pala, E. V. Brunt, D. J. Lichtenwalner, G-Y Wang, J. Richmond, M. O′Loughlin, S. Ryu, S. T. Allen, and A. A. Burk (2014). Silicon carbide power MOSFETs: breakthrough performance from 900 V up to 15 kV, Proc. of ISPSD’26, 79-82.
[12] A. M. S. Al-bayati, S. S. Alharbi, S. S. Alharbi, and M. Matin (2017). A comparative design and performance study of a non-isolated DC-DC buck converter based on Si-MOSFET/Si-diode, SiC-JFET/SiC-schottky diode, and GaN-transistor/SiC-Schottky diode power devices, Proc. of 2017 North American Power Symp..
[13] X. Li, X. Tong, A. Q. Huang, H. Tao, K. Zhou, Y. F. Jiang, J. N. Jiang, X. C. Deng, X. She, B. Zhang, Y. Zhang, and T. Qi (2018). SiC trench MOSFET with integrated self-assembled three-level protection schottky barrier diode, IEEE Trans. Electron Devices, 65 (1), 347-351.
[14] K. Tian, A. Hallén, J. Qi, S. Ma, X. Fei, A. Zhang, and W. Liu (2019). An improved 4H-SiC trench-gate MOSFET with low on-resistance and switching loss, IEEE Trans. Electron Devices, 66 (5), 2307-2313.
[15] H. Takaya, J. Morimoto, K. Hamada, T. Yamamoto, J. Sakakibara, Y. Watanabe, and N. Soejima (2013). A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics, Proc. of ISPSD’25, 43-46.
[16] M. Darwish, C. Yue, K. H. Lui, F. Giles, B. Chan, K.i. Chen, D. Pattanayak, Q. Chen, K. Terrill, and K. Owyang (2003). A new power W-gated trench MOSFET (WMOSFET) with high switching performance, Proc. of ISPSD’15, 24-27.
[17] M. A. Gajda, S. W. Hodgkiss, L. A. Mounfield, N. T. Irwin, G. E. J. Koops, and R. V. Dalen (2006). Industrialisation of resurf stepped oxide technology for power transistors, Proc. of ISPSD’18, 109-112.
[18] Koops, Hijzen, Hueting, and I. Zandt (2006). RESURF stepped oxide (RSO)MOSFET for 85V having a record-low specific on-resistance, Proc. of ISPSD’18, 185-188.
[19] B. J. Baliga (1999). Power semiconductor devices having improved high frequency switching and breakdown characteristics, U.S. Patent 5998833.
[20] J. Zeng (2004). Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and Miller charge, U.S. Patent 6683346.
[21] P. Goarin, G. E. J. Koops, R. van Dalen, C. L. Cam, and J. Saby (2007). Split-gate resurf oxide (RSO) MOSFETs for 25V applications with record low gate-to-drain charge, Proc. of ISPSD’19, 61-64.
[22] K. Vershinin, P. Moens, F. Bauwens, E. M. S. Narayanan, and M. Tack (2009). A new method to improve tradeoff performance for advanced power MOSFETs, IEEE Electron Device Lett., 30 (4), 416-418.
[23] K. Kobayashi, M. Sudo, and I. Omura (2018). Power loss analysis of 60 V trench field-plate MOSFETs utilizing structure based capacitance model for automotive application, Proc. of CIPS 2018, 122-127.
[24] K. Kobayashi, M. Sudo, and I. Omura (2018). Structure-based capacitance modeling and power loss analysis for the latest high-performance slant field-plate trench MOSFET, Proc. of Jpn. J. Appl. Phys, 1-8.
[25] S. T. Peake, P. Rutter, S. Hodgskiss, M. Gajda, and N. Irwin (2008). A fully realized ‘field balanced’ trenchMOS technology, Proc. of ISPSD’20, 28-31.
[26] Y. Wang, H. F. Hu, Z. Dou, and C. H. Yu (2014). Way of operation to improve performance for advanced split-gate resurf stepped oxide UMOSFET, IET Power Electron., 7 (12), 2964-2968.
[27] 鄧傑文 (2015). V-grooved edge termination design for high voltage VDMOSFET. 東海大學電機工程學系, Taiwan.
[28] M. L. Tarng (1981). On-resistance characterization of VDMOS power transistors, Proc. of IEDM 1981, 429-433.
[29] 簡鳳佐 (2014)。功率金氧半電晶體(Power MOSFET)之簡介，台灣電子材料與元件協會 功率電子專刊I，20 (1)，5-20。
[30] R. S. Saxena and M. J. Kumar (2012). Polysilicon spacer gate technique to reduce gate charge of a trench power MOSFET, IEEE Trans. Electron Devices, 59 (3), 738-744.
[31] R. J. E. Hueting, E. A. Hijzen, A. Heringa, A. W. Ludikhuize, and M. A. A. Zandt (2004). Gate-drain charge analysis for switching in power trench MOSFETs, IEEE Trans. Electron Devices, 51 (8)1323-1330.
[32] C. Park, S. Havanur, A. Shibib, and K. Terrill (2016). 60 V rating split gate trench MOSFETs having best-in-class specific resistance and figure-of-merit, Proc. of ISPSD’28, 387-390.
[33] H. Takaya, K. Miyagi, K. Hamada, Y. Okura, N. Tokura, and A. Kuroyanagi (2005). Floating island and thick bottom oxide trench gate MOSFET (FITMOS)-a 60V ultra low on-resistance novel MOSFET with superior internal body diode, Proc. of ISPSD’17, 1-4.
[34] Y. Chen, Y. C. Liang, and G. S. Samudra (2007). Design of gradient oxide-bypassed superjunction power MOSFET devices, IEEE Trans. Power Electronics, 22 (4), 1303-1310.
[35] K. Kobayashi, H. Kato, T. Nishiguchi, S. Shimomura, T. Ohno, T. Nishiwaki, K. Aida, K. Ichinoseki, K. Oasa, and Y. Kawaguchi (2019). 100-V class two-step-oxide field-plate trench MOSFET to achieve optimum RESURF effect and ultralow on-resistance, Proc. of ISPSD’31, 99-102.
[36] K. Kobayashi, T. Nishiguchi, S. Katoh, T. Kawano, and Y. Kawaguchi (2015). 100 V class multiple stepped oxide field plate trench MOSFET (MSO-FP-MOSFET) aimed to ultimate structure realization, Proc. of ISPSD’27, 141-144.
[37] C. Park, M. Azam, G. Dengel, A. Shibib, and K. Terrill (2019). A new 200 V dual trench MOSFET with stepped oxide for ultra low RDS(on), Proc. of ISPSD’31, 95-98.
[38] B. J. Daniel, C. D. Parikh, and M. B. Patil (2002). Modeling of the coolMOS/sup TM/ transistor - part I: device physics, IEEE Trans. Electron Devices, 49 (5), 916-922.
[39] L. Lorenz, G. Deboy, A. Knapp, and M. Marz (1999). COOLMOS/sup TM/-a new milestone in high voltage power MOS, Proc. of ISPSD’11, 3-10.
[40] P. N. Kondekar, C. D. Parikh, and M. B. Patil (2002). Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer, Proc. of PESC’33, 1769-1775.
[41] Q. Wang, M. Li, J. Sharp, and A. Challa (2007). The effects of double-epilayer structure on threshold voltage of ultralow voltage trench power MOSFET devices, IEEE Trans. Electron Devices, 54 (4), 833-839.
[42] M. Li, A. Crellin, I. Ho, and Q. Wang (2008). Double-epilayer structure for low drain voltage rating n-channel power trench MOSFET devices, IEEE Trans. Electron Devices, 55 (7), 1749-1755.
[43] B. J. Daniel, C. D. Parikh, and M. B. Patil (2002). Modeling of the coolMOS/sup TM/ transistor—Part I: Device physics, IEEE Trans. Electron. Devices, 49 (5), 916-922.
[44] H. Yamaguchi, Y. Urakami, and J. Sakakibara (2006). Breakthrough of on-resistance Si limit by Super 3D MOSFET under 100V breakdown voltage, Proc. of ISPSD’18.
[45] Y. Hattori, K. Nakashima, M. Kuwahara, T. Yoshida, S. Yamauchi, and H. Yamaguchi (2004). Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling, Proc. of ISPSD’16, 189-192.
[46] Y. Weber, F. Morancho, J. Reynes, and E. Stefanov (2008). A new optimized 200V low on-resistance power FLYMOSFET, Proc. of ISPSD’20, 149-152.
[47] Y. Miura, H. Ninomiya, and K. Kobayashi (2005). High performance superjunction UMOSFETs with split p-columns fabricated by multi-ion-implantations, Proc. of ISPSD’17, 1-4.
[48] R. V. Dalen and C. Rochefort (2004). Electrical characterization of vertical vapor phase doped (VPD) RESURF MOSFETs, Proc. of ISPSD’16, 451-454.
[49] T. Nitta, T. Minato, M. Yano, A. Uenisi, M. Harada, and S. Hine (2000). Experimental results and simulation analysis of 250V super trench power MOSFET (STM), Proc. of ISPSD’12, 77-80.
[50] T. Kurosaki, H. Shishido, M. Kitada, K. Oshima, S. Kunori, and A. Sugai (2003). 200V multi RESURF trench MOSFET (MR-TMOS), Proc. of ISPSD’15, 211-214.
[51] X. B. Chen, P. A. Mawby, K. Board, and C.A.T. Salamab (1998). Theory of a novel voltage-sustaining layer for power devices, Microelectron. J., 29 (12), 1005-1011.
[52] Y. Chen, Y. C. Liang, and G. S. Samudra (2005). Theoretical analyses of oxide-bypassed superjunction power metal oxide semiconductor field effect transistor devices. Jpn. J. Appl. Phys., 44(2), 847-856.
[53] 友達光電股份有限公司-顯示器解決方案-低溫多晶矽顯示器製程，網址:
https://reurl.cc/0o0aZo
[54] S. D. Brotherton (1995). Polycrystalline silicon thin film transistors, Semicond. Sci. Technol., 10 (6), 721-738.
[55] T. J. Konno and R. Sinclair (1994). Metal-contact induced crystallization of semiconductors, Materials Science Engineering, 179-180, 426-432.
[56] S. F. Gong (1987). Al-doped and Sb-doped Polycrystalline silicon obtained by means of metal-induced crystallization, J. Appl. Phys., 62 (9), 3726-3732.
[57] L. Hultman, A. Robertsson, H. T. G. Hentzell, I. Engstrom, and P. A. Psaras (1987). Crystallization of amorphous silicon during thin-film gold reaction, J. Appl. Phys., 62 (9), 3647-3655.
[58] N. Kubo, N. Kusummoto, T. Inushima, and S. Yamazaki (1994). Characterization of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method, IEEE Trans. Electron Devices, 41 (10), 1876-1879.
[59] G. K. Giust and T. W. Sigmon (1998). High-performance thin-film transistors fabricated using excimer laser processing and grain engineering, IEEE Trans. Electron Devices, 45 (4), 925-932.
[60] M. Cao, S. Talwar, K. J. Kramer, T. W. Sigmon, and K. C. Saraswat (1996). A high-performance Polysilicon thin-film transistor using XeCl excimer laser crystallization of pre-patterned amorphous Si films, IEEE Trans. Electron Devices, 43 (4), 561-567.
[61] A. G. Lewis, D. D. Le, and R. H. Bruce (1992). Poly silicon TFT circuit design and performance, IEEE J. Solid-State Circuits, 27 (12), 1833-1841.
[62] K. R. Olasupo and M. K. Hatalis (1996). Leakage current mechanism in sub-micron Polysilicon thin-film transistors, IEEE Trans. Electron Devices, 13 (8), 1218-1223.
[63] S. M. Sze (1982). Physics of Semiconductor Devices, 2nd Edition, New York: Wiley-Interscience.
[64] G. Vincent, A. Chantre, and D. Bois (2008). Electric field effect on the thermal emission of traps in semiconductor junctions, J. Appl. Phys., 50 (8), 5484-5487.
[65] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-meimand (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits, Proc. of IEEE, 91 (2), 305-327.
[66] S. Wolf (1995). Silicon processing for the VLSI ERA, volume 3: the submicron MOSFET, Lattice Pr.
[67] K. R. Olasupo and M. K. Hatalis (1996). Leakage current mechanism in sub-micron Polysilicon thin-film transistors, IEEE Trans. Electron Devices, 13 (8), 1218-1223.
[68] G. A. Bhat, Z. Jin, H. S. Kwok, and M. Wong (1999). Effects of longitudinal grain boundaries on the performance of MILC-TFT’s, IEEE Electron Device Lett., 20 (2), 97-99.
[69] J. G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Banerjee (1985). Anomalous leakage current in LPCVD Polysilicon MOSFET’s, IEEE Trans. Electron Devices, 32 (9), 1878-1884.
[70] K. R. Olasupo and M. K. Hatalis (1996). Leakage current mechanism in sub-micron Polysilicon thin-film transistors, IEEE Trans. Electron Devices, 13 (8), 1218-1223.
[71] M. Lack, I. W. Wu, T. J. King, and A. G. Lewis (1993). Analysis of leakage currents in Poly silicon thin film transistors, Proc. of IEDM 1993, 385-388.
[72] A. T. Hatzopoulos, D. H. Tassis, N. H. Hastas, C. A. Dimitriadis, and G. Kamarinos (2005). An analytical hot-carrier induced degradation model in Polysilicon TFTs, IEEE Trans. Electron Devices, 52 (10), 2182-2187.
[73] L. Mariucci, G. Fortunato, A. Bonfiglietti, M. Cuscuna, A. Pecora, and A. Valletta (2004). Polysilicon TFT structures for kink-effect suppression, IEEE Trans. Electron Devices, 51 (7), 1135-1142.
[74] M. Hack and A.G. Lewis (1991). Avalanche induced effects in Polysilicon thin-film transistors, IEEE Electron Device Lett., 12 (5), 203-205.
[75] A. Valletta, P. Gaucci, L. Mariucci, and G. Fortunato (2007). Modeling velocity saturation and kink effects in p-channel Polysilicon thin film transistors, Thin Solid Films, 515 (19), 7417-7421.
[76] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio (1997). Floating body effects in Polysilicon thin-film transistors, IEEE Trans. Electron Devices, 44 (12), 2234-2241.
[77] D. D. Venutoa and M. J. Ohletzb (2003). Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits, Microelectronics J., 34 (10), 889-895.
[78] S. Bindra, S. Haldar, and R. S. Gupta (2003). Modeling of kink effect in Polysilicon thin film transistor using charge sheet approach, Solid-State Electron., 47 (4), 645-651.
[79] J. I. Han, G. Y. Yang, and C. H. Han (1999). A new self-aligned offset staggered Polysilicon thin-film transistor. IEEE Electron Device Lett., 20 (8), 381-383.
[80] C. A. Dimitriadis and M. Miyasaka (2000). Performance enhancement of offset gated Polysilicon thin-film transistors, IEEE Electron Device Lett., 21 (12), 584-586.
[81] K. Ohgata, Y. Mishima, and N. Sasaki (2000). A new dopant activation technique for Poly-Si TFTs with a self-aligned gate-overlapped LDD structure, Proc. of IEDM 2000, 205-208.
[82] S. D. Zhang, R. Han, and M. J. Chan (2001). A novel self-aligned bottom gate Poly-Si TFT with in-situ LDD, IEEE Electron Device Lett., 22 (8), 393-395.
[83] I. S. Kang, S. H. Han, and S. K. Joo (2008). Novel offset-gated bottom gate Poly-Si TFTs with a combination structure of ultrathin channel and raised source/drain, IEEE Electron Device Lett., 29 (3), 232-234.
[84] H. C. Lin, C. M. Yu, C. Y. Lin, K. L. Yeh, T. Y. Huang, and T. F. Lei (2001). A novel thin-film transistor with self-aligned field induced drain, IEEE Electron Device Lett., 22 (1), 26-28.
[85] A. A. Orouji and M. J. Kumar (2006). Leakage current reduction techniques in Poly-Si TFTs for active matrix liquid crystal displays: a comprehensive study, IEEE Trans. Device and Materials Reliability, 6 (2), 315-325.
[86] K. Tanaka, H. Arai, and S. Kohda (1988). Characteristics of offset-structure polycrystalline-silicon thin-film transistors, IEEE Electron Device Lett., 9 (1), 23-25.
[87] D. Ryu, I. Myeong, J. K. Lee, M. Kang, and J. Jeon (2019). Investigation of gate sidewall spacer optimization from off-state leakage current perspective in 3-nm node device, IEEE Trans. Electron Devices, 66 (6), 2532-2537.
[88] Shengdong Zhang, Ruqi Han, Johnny K. O. Sin, and Mansun Chan (2001). A novel self-aligned double-gate TFT technology, IEEE Trans. Electron Devices, 22 (11), 530-532.
[89] M. C. Lee and M. K. Han (2004). Poly-Si TFTs with asymmetric dual-gate for kink current reduction, IEEE Electron Device Lett., 25 (1), 25-27.
[90] X. Luo, J. Wei, X. Shi, K. Zhou, R. Tian, B. Zhang, and Z. Li (2014). Novel reduced on-resistance LDMOS with an enhanced breakdown voltage, IEEE Transactions on Electron Devices, 61 (12), 4304-4308.
[91] 陳志強(2004)。LTPS低溫複晶矽顯示器技術，全華科技圖書股份有限公司，2-05~2-07。
[92] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. S. Lin, B. H. Tseng, J. H. Shy, S. M. Sze, C. Y. Chang, and C. H. Lien (2007). A novel nanowire channel Poly-Si TFT functioning as transistor and nonvolatile SONOS memory, IEEE Electron Device Lett., 28 (9), 809-811.
[93] N. I. Lee, J. W. Lee, H. S. Kim, and C. H. Han (1999). High-performance EEPROM’s using n-and p-channel Polysilicon thin-film transistors with electron cyclotron resonance N2O-plasma oxide, IEEE Electron Device Lett., 20 (1), 15-17.
[94] J. H. Oh, H. J. Chung, N. I. Lee, and C. H. Han (2000). A high-endurance low-temperature Polysilicon thin-film transistor EEPROM cell, IEEE Electron Device Lett., 21 (6), 304-306.