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研究生:王志哲
研究生(外文):WANG, ZHI-ZHE
論文名稱:溝槽式分離閘極功率金氧半場效電晶體之三層磊晶層設計與利用等電位汲極改善扭結效應之雙閘極複晶矽薄膜電晶體設計
論文名稱(外文):Design of Split-Gate Trench Power MOSFET with Triple EPI and a Double Gate Poly-Si Thin Film Transistor Design by Adding a Equipotential Drain to Reduce Kink Effect
指導教授:簡鳳佐簡鳳佐引用關係
指導教授(外文):CHIEN, FENG-TSO
口試委員:簡鳳佐邱顯欽陳啟文
口試委員(外文):CHIEN, FENG-TSOCHIU, HSIEN-CHINCHEN, CHII-WEN
口試日期:2020-07-13
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:140
中文關鍵詞:溝槽分離式閘極功率金氧半場效電晶體多層磊晶層特定導通電阻複晶矽薄膜電晶體雙閘極等電位汲極分離通道ISE模擬軟體
外文關鍵詞:split-gate trench power MOSFETmultiple epitaxial layersspecific on-resistancepoly-Si TFTdouble gateequipotential drainsplit channelISE-TCAD
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第一單元以功率元件為主
功率金氧半場效應電晶體主要用於電力設備的電能變換和電路控制,是進行電能(功率)處理的核心元件,包括電源供應器、通訊設備、汽車電子、工業電子、消費性電子及顯示器等,尤其是汽車電子產業快速發展,使得該元件需求快速增加。對於功率元件而言,兩項最重要的特性是崩潰電壓(breakdown voltage)與特定導通電阻(Ron,sp),由於這兩個參數是互相影響的,因此要同時擁有高耐壓和低導通電阻相當不易。典型的功率元件功能包括變頻、變壓、變流、功率放大和功率管理,除保證設備正常運行外,功率元件還起到節能的作用,為了降低功率元件的傳導損耗,低導通電阻元件的研究成為各研究者的競爭目標。
在此,我們提出並研究了具有不同磊晶層(EPI)的150V額定電壓溝槽式分離閘極(SGT)功率金氧半場效電晶體(MOSFET)。為了降低150V SGT功率MOSFET的Ron,sp,我們使用多種EPI結構來設計和比較基於相同製造工藝的單層EPI和雙層EPI元件。我們發現,雙層EPI結構的底層EPI可以用來提供崩潰電壓,並且可以透過調整頂層EPI以降低Ron,sp,因此,雙層EPI元件比單層EPI元件具有更大的靈活性以實現更低的Ron,sp。然而,當所需電壓超過100V時,雙層EPI結構的Ron,sp不再滿足我們的預期,因此我們設計並研究了三層EPI結構,以在不犧牲崩潰電壓的情形下降低Ron。我們使用ISE-TCAD模擬軟體透過調整每層EPI的厚度與電阻率來研究150V SGT功率元件。最後,150V三層EPI元件的模擬Ron值,相較於雙層結構,可擁有81.67%的降低;相較於單層結構,則可擁有38.13%的降低。

第二單元以薄膜電晶體為主
複晶矽薄膜電晶體(Poly-Si TFT)目前被廣泛的運用在面板相關產品上,如主動式液晶顯示器(AMLCD)、像素開關以及外圍驅動電路。相較於非晶矽薄膜電晶體,複晶矽薄膜電晶體可提供較高的載子遷移率和較大的驅動電流,對於大尺寸的顯示器而言可展現更快的開關反應時間和較高的電流來驅動畫素。然而,由於在較高汲極電壓操作下,傳統型複晶矽薄膜電晶體在靠近汲極與通道接面端會產生高電場以及玻璃基板因無基極端點易產生寄生BJT正回授效應,且高電場又是造成離子碰撞的主要原因,這導致了許多不理想效應,如漏電流效應、熱載子效應及扭結效應等而限制其使用範圍。
因此,我們利用一個在近汲極端通道周圍空間等電位結構的設計,提出“利用等電位汲極改善扭結效應之雙閘極複晶矽薄膜電晶體設計”來改善不理想效應,在此設計中我們將薄膜電晶體元件應用雙閘極(double gate)、等電位汲極(equipotential drain)以及分離式通道(split channel)的概念設計並配合ISE-TCAD來預估其特性。此新式結構經過我們的模擬分析,由於採用double gate,使得元件增加約兩倍的開電流。而equipotential drain的設計藉由該處等電位的結構,可以使得近汲極處通道內電壓差趨近於零進而降低該處之電場,還可以使電流遠離高電場區域以改善汲極端的離子碰撞。另外,split channel的設計可以使通道中的N+抑制扭結效應之正回授的發生,因而提升元件的崩潰電壓。此結構不同於過去的結構設計,不僅有效改善汲極端電場,緩和元件扭結效應並降低其離子碰撞產生率使其元件的使用耐壓大幅上升,並可以改善元件之漏電流。在光罩數製程成本的設計上與傳統雙閘極結構相同,不需額外昂貴的製程,不但符合了降低光罩製作成本設計的預算,更能符合市場所需之趨勢。
The first part is based on power components.
Power metal-oxide-semiconductor field-effect transistors are mainly used for power conversion and circuit control of power equipment and are the core components for power processing, including power supplies, communication equipment, automotive electronics, industrial electronics, consumer electronics, and displays. In particular, the rapid development of the automotive electronics industry has led to a rapid increase in demand for this component. For power devices, the two most important characteristics are the breakdown voltage and specific on-resistance (Ron,sp). Since these two parameters affect each other, it is difficult that they have both high breakdown voltage and low on-resistance. Typical power device functions include frequency conversion, voltage transformation, current conversion, power amplification, and power management. In addition, to ensure the normal operation of the device, the power device also plays a role in saving energy. In order to reduce the conduction loss of power devices, the research of low on-resistance elements has become a competitive goal for various researchers.
Therefore, a rating voltage of 150 V split-gate trench (SGT) power metal-oxide-semiconductor field-effect transistor (power MOSFET) with different epitaxial layers have been proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 V SGT power MOSFET, we use multiple epitaxies (EPIs) structure to design and compared other single and double EPIs devices based on the same fabrication process. We found the bottom epitaxy (EPI) layer of a double EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double EPIs device has more flexibility to achieve a lower Ron,sp than the single EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double EPIs device is no longer satisfying our expected. A triple EPIs structure was designed and studied to reduce its Ron without sacrificing the breakdown voltage. We used Integrated System Engineering-Technology Computer Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple EPIs device is only 81.67 and 38.13 % of that for the double EPIs and single one structure, respectively.

The second part is based on thin film transistor.
Poly-Si TFTs are currently widely used in panel related products such as active matrix liquid crystal displays (AMLCDs), pixel switches, and peripheral driver circuits. Compared to amorphous silicon thin film transistors, polycrystalline silicon thin film transistors provide higher carrier mobility and larger drive current. Exhibiting faster switching reaction time and higher current to drive the pixels for large size displays. However, due to the higher voltage operation, the conventional polycrystalline silicon thin film transistor generates a high electric field near the junction of the drain and the channel, and the glass substrate is prone to parasitic BJT positive feedback effect due to the no base. High electric field is the main cause of impact ionization, which leads to many non-ideal effects, such as leakage current effect, hot carrier effect, and kink effect, which limits its range of use.
Therefore, we used a design a space equal voltage at channel/drain area in a TFT structure, and proposed “A Double Gate Poly-Si Thin Film Transistor Design by Adding a Equipotential Drain to Reduce Kink Effect” to improve the undesirable effect of thin film transistors. In this design, we applied double gate, equipotential drain, and split channel into thin film transistor component, and combined with ISE-TCAD simulation to predict its characteristics. This new structure had been analyzed by our simulation, due to the design of the double gate structure, the on-current of the device had been increased about two times. The design of the equipotential drain structure can make the voltage difference close to zero and reduce the electric field in the channel near the drain electrode. It could also keep the current away from the high electric field region to reduce the impact ionization. In addition, the design of the split channel allowed the N+ in the channel to suppress the positive feedback of the kink effect, thus increasing the breakdown voltage of the component. This structure is different from the previous structure design, not only effectively reduces the drain electric field, alleviates the kink effect of the device, and reduces the rate of impact ionization. Which greatly increases the breakdown voltage of the device, but also can improve the leakage current of the device. The design cost of the mask number process is as same as the traditional double gate structure, and no extra expensive process is required. It not only conforms the budget for reducing the design cost of the mask, but also conforms the trend required by the market.
誌謝 i
摘要 ii
Abstract v
目錄 viii
圖目錄 x
表目錄 xiv

單元一 溝槽式分離閘極功率金氧半場效電晶體之三層磊晶層設計
第一章 緒論 1
1.1 研究背景 2
1.2 常見之POWER MOSFET簡介 4
1.3 SPLIT-GATE TRENCH POWER MOSFET介紹 6
1.4 POWER MOSFET機制 7
1.5 研究動機 16
第二章 文獻探討 17
2.1 利用氧化物設計提高元件性能 17
2.2 利用改變材料提高元件性能 19
2.3 利用磊晶層設計提高元件性能 20
第三章 元件設計與模擬流程 21
3.1 元件結構 21
3.2 模擬製程步驟 22
第四章 模擬結果與分析 27
4.1 三層磊晶層之SGT POWER MOSFET分析 27
4.2 相同磊晶層厚度之SGT POWER MOSFET分析 30
4.3 150 V額定電壓之SGT POWER MOSFET分析 35
4.4 200 V額定電壓之SGT POWER MOSFET分析 41
第五章 結論 44

單元二 利用等電位汲極改善扭結效應之雙閘極複晶矽薄膜電晶體設計
第一章 緒論 45
1.1 研究背景 46
1.2 薄膜電晶體簡介 48
1.3 複晶矽薄膜電晶體關鍵技術 51
1.4 複晶矽薄膜電晶體之不理想效應及其改善方式 54
1.5 研究動機 61
第二章 文獻探討 62
2.1 利用雙閘極提升元件飽和電流 62
2.2 利用分離式閘極改善扭結效應 64
2.3 利用等電位改善高電場 66
第三章 元件設計與模擬流程 67
3.1 元件結構 67
3.2 模擬製程步驟 69
第四章 模擬結果與分析 72
4.1 電位分析 74
4.2 電場分析 76
4.3 離子碰撞分析 80
4.4 電流分析 82
4.5 漏電流分析 84
4.6 輸出特性曲線分析 88
4.7 頂閘極與等電位汲極間之N+長度分析 89
4.8 等電位汲極長度分析 92
第五章 實驗結果與分析 95
5.1光罩設計 95
5.2 實驗製程步驟 99
5.3 元件之SEM分析 101
第四節 電性參數萃取 104
第五節 量測結果與討論 108
第六章 結論 112
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