臺灣博碩士論文加值系統

本論文使用了維也納公司所研發的Global TCAD Solutions(GTS) TCAD模擬軟體，研究矽奈米線電晶體與鰭式場效電晶體載子遷移率。
本論文第一部份模擬了四種奈米線電晶體的通道截面形狀：圓形、三角形、正方形與菱形，其中我們又將菱形分成無偏轉和右旋60度兩種通道截面角度來觀察電子遷移率的變化，從模擬得知以矽為通道材料時，所有的截面形狀都顯示在模擬較大的通道截面面積時，在[100]通道方向會有較大的電子遷移率，而在模擬較小的通道截面面積時，則在[110]通道方向會有較大的電子遷移率。第二部份，我們在模擬鰭式場效電晶體時加入六種方向的應力，發現X軸和YZ軸施加應力對載子遷移率有較多的變化。

This master thesis uses Global TCAD Solutions (GTS) TCAD simulation software developed by a company from Vienna to study the carrier mobility of silicon nanowire transistors and fin field effect transistors (FinFET).
The first part of this master thesis simulates the channel cross-sectional shapes of four types of nanowire transistors, including circle, triangle, square, and diamond. The diamond shape is further divided into two channel cross-sectional angles of non-deflection and right-side 60 degrees to observe the change of electrons mobility. From the simulation when silicon is used as the channel material, all the cross-sectional shapes show that, when a larger channel cross-sectional area is simulated, there will be better electron mobility in the [100] channel direction, while the electron mobility will be better in the [110] channel direction when the cross-sectional area of the channel is small. In the second part, stress in six directions is added when simulating a FinFET. It is found that the X-axis and YZ-axis applied stress has more gain in the carrier mobility.

誌謝 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 導論 1
1-1研究動機與背景 1
1-2文獻回顧 2
第二章 應變理論分析 5
2-1應力與應變介紹 5
2-2應變矽的材料性質與載子傳輸特性 7
第三章 能帶結構與遷移率計算理論 9
3-1 能帶結構 9
3-1.1 奈米線電晶體能帶模擬 9
3-1.2 k．p微擾法 14
3-1.3 3D狀態密度(Density of States) 15
3-1.4 2D狀態密度(Density of States) 16
3-1.5 1D狀態密度(Density of States) 17
3-2 Schrödinger equation 18
3-3 Poisson equation 19
3-4散射機制理論 20
3-4.1 Optical phonon scattering (ODP) 20
3-4.2 Acoustic phonon scattering (ADP) 21
3-4.3 Surface roughness scattering (SRS) 22
3-5 GTS-VSP操作說明及模組介紹 24
第四章 結果與討論 30
4-1 n-type矽奈米線電晶體電子遷移率計算 30
4-1.1截面尺寸對遷移率之影響 36
4-1.2相同通道截面面積之電子遷移率比較 37
4-1.3表面粗糙度散射參數對電子遷移率之影響 39
4-2 矽鰭式場效應電晶體載子遷移率計算 40
4-2.1 n-type矽鰭式場效應電晶體電子遷移率 41
4-2.2 p-type矽鰭式場效應電晶體電洞遷移率 43
第五章 結論與未來展望 45
5-1 結論 45
5-2 未來展望 46
參考文獻 47

[1] E. B. Ramayya, D. Vasileska, S. M. Goodnick, and I. Knezevic, “Electron transport in silicon nanowires: The role of acoustic phonon confinement and surface roughness scattering,” Journal of Applied Physics, vol. 104, pp. 063711, Sep.2008.
[2] N. Neophytou, and H. Kosina, “Strong anisotropy and diameter effects on the low-field mobility of silicon nanowires,” 2011 International Conference on Simulation of Semiconductor Processes and Devices, doi. 10.1109, Sep. 2011.
[3] Y. M. Niquet, C. Delerue, D. Rideau, and B. Videau , “Fully Atomistic Simulations of Phonon-Limited Mobility of Electrons and Holes in ⟨001⟩-, ⟨110⟩-, and ⟨111⟩ -Oriented Si Nanowires,” IEEE Transactions on Electron Devices, vol. 59, pp. 1480 - 1487, May. 2012.
[4] C. Buran , M. G. Pala , M. Bescond , M. Dubois , and M. Mouis , “Three- Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs,” IEEE Transactions on Electron Devices, vol. 56, pp. 2186 – 2192, Oct. 2009.
[5] A. K. Buin, A. Verma and M. P. Anantram, “Carrier-phonon interaction in small cross-sectional silicon nanowires,” Journal of Applied Physics, vol. 104, pp. 053716, Jun. 2008.
[6] R. Kotlyar, T. D.Linton, R. Rios, M. D. Giles, and S. M. Cea, “Does the low hole transport mass in 〈110〉 and 〈111〉 Si nanowires lead to mobility enhancements at high field and stress: A self-consistent tight-binding study,” Journal of Applied Physics, vol. 111, pp. 123718, Jun. 2012.
[7] S. Dhar, H. Kosina, V. Palankovski, E. Ungersboeck and S. Selberherr, “Electron mobility model for strained-Si devices,” IEEE Trans. Electron Devices, vol. 52, pp. 527-533, Apr. 2005
[8] S. Dhar, E. Ungersbock, H. Kosina, T. Grasser, and S. Selberherr, “Electron Mobility Model for 〈110〉 Stressed Silicon Including Strain-Dependent Mass,” IEEE Transactions on Nanotechnology, vol. 6, pp. 97 – 100, Jan. 2007
[9] J. Song, B. Yu, W. Xiong, and Y. Taur, “Gate-Length-Dependent Strain Effect in n- and p-Channel FinFETs,” IEEE Transactions on Electron Devices, vol. 56, pp. 533-536, Mar. 2009.
[10] K. Uchida, A. Kinoshita, and M. Saitoh, “Carrier transport in (110) nMOSFETs: Subband structures non-parabolicity mobility characteristics and uniaxial stress engineering,” 2006 International Electron Devices Meeting, doi. 10.1109, Dec. 2006.
[11] C. F. Lee, R. Y. He, K. T. Chen, S. Y. Cheng, and S. T. Chang, “Strain engineering for electron mobility enhancement of strained Ge NMOSFET with SiGe alloy source/drain stressors,” Microelectronic Engineering, vol. 138, no. 4, pp. 12-16, Jan. 2015.
[12] K. H. Cho, K. H. Yeo, Y. Y. Yeoh, S. D. Suk, M. Li, J. M. Lee, M. S. Kim, D. W. Kim, D. Park, B. H. Hong, Y. C. Jung, and S. W. Hwang, “Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, vol. 92, pp. 052102, Jan.2008.
[13] N. Neophytou, Abhijeet Paul, Mark S. Lundstrom, and Gerhard Klimeck, “Bandstructure Effects in Silicon Nanowire Electron Transport,” IEEE Transactions on Electron Devices., vol. 55, no. 6, pp. 1286-1297, Jun.2008.
[14] N. Neophytou, and G. Klimeck, “Design space for low sensitivity to size variations in [110] PMOS nanowire devices: The implications of anisotropy in the quantization mass,” Nano Lett., vol. 9, no. 2, pp. 623-630, Jan.2009.
[15] S. Poli, and M. G. Pala, “Channel-Length Dependence of Low-Field Mobility in Silicon-Nanowire FETs,” IEEE Electron Device Letters, vol. 30, pp. 1212 - 1214, Nov. 2009.
[16] J. Wang, E. Polizzi, A. Gosh, S. Datta and M. Lundstrum, “Theoretical investigation of surface roughness scattering in silicon nanowire transistors,” Applied Physics Letters, vol. 87, no. 4, pp. 043101, Jul. 2005.