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研究生:吳忠翰
研究生(外文):Jhong-HanWu
論文名稱:利用通道表面工程改善氮氧化鋁鋅薄膜電晶體特性之研究
論文名稱(外文):Improving Electrical Performance of AZON Thin-Film Transistors with Channel Surface Engineering
指導教授:王水進
指導教授(外文):Shui-Jinn Wang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:微電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:122
中文關鍵詞:氮氧化鋁鋅通道表面工程薄膜電晶體共濺鍍通道薄化
外文關鍵詞:Al-dopedZnONChannel surfaceCo-sputteringThin film transistor
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本論文提出以共濺鍍技術適當摻雜鋁(Al)改善氮氧化鋁鋅(ZnON)薄膜(稱AZON)電晶體(Thin film transistors, TFTs)之通道層品質,再利用通道層增厚與通道表面工程(Channel surface engineering, CSE)提升元件驅動能力與降低其關閉功耗,且針對元件之表面結構以模擬進行設計與分析,並由實驗進行元件製作、電性量測與分析研究。
本論文主要分三個部分,第一部分為模擬通道厚度增加與CSE 通道表面結構之電性分析與設計,並提出蕭基型(Schottky type)與金氧半型(MOS type)兩種表面結構,並進行結構參數(包括位置、功函數與寬度等)對表面結構效應影響之探討。觀察不具CSE之下閘極的通道層增厚模擬結果,通道層厚度從20 nm增加至40 nm得到導通電流從0.39 mA增加為8.5 mA之效益。以Schottky type完成CSE位置效應之分析,其中以至於通道中心(x_0=0.5L)之Schottky type CSE最具空乏效益。採用最佳位置探討不同功函數以及不同寬度對於元件特性的影響,結果以具蕭基金屬Pt並採用W_x=0.25L及Floating條件的Schottky type擁有最大的電流開關比(〖5.87×10〗^16)以及最佳的次臨界擺幅(subthreshold swing)(78 mV/dec)。此外,於探討MOS type CSE的計算結果表明,在表面結構中介電層的幫助下,透過偏壓得以調變通道空乏的程度。最後進行通道厚度最大化的模擬,以量化具CSE於導通電流的提升效益與關閉電流的抑制能力,採用最佳空乏能力與特性的Schottky type CSE(具蕭基金屬Pt並採用W_x=0.25L及Floating條件),於此條件之通道厚度可由40 nm增加至44 nm並使導通電流高出無CSE且厚度為20 nm之傳統TFT約10.76倍,同時電流開關比仍具有約34.4倍的增益。
第二部分為利用共濺鍍技術完成最適化條件之通道薄膜。由於ZnON為單一金屬陽離子,其電子於導帶傳導時能受到較低的能位障影響,以及Zn3N2中的電子擁有較小的有效質量(m_e≈ 0.19 m_0),故展現出較高的載子移動率,所測得霍爾移動率與載子濃度分別為108.2 cm^2/V∙s與〖1.88×10〗^18 cm^(-3)。有鑑於ZnON中Zn-N之鍵結解離能(Bonding dissociation energy, BDE)約為160 kJ∙mol^(-1),使得N原子容易逸散形成氮空缺,以高化學活性之Al(BDE =512 kJ∙mol^(-1))利用共濺鍍技術進行摻雜實現Al-ZnON (AZON)改善氮空缺提升薄膜穩定性,其中最適化摻雜比例經由XPS分析獲得為Al(11.1%)-ZnON,並具備霍爾移動率與載子濃度分別為84.1 cm^2/V∙s與〖3.09×10〗^18 cm^(-3),最後於大氣中放置5天後其霍爾移動率僅有少於5%的衰退。另外,Al(11.1%)-ZnON經過UV-VIS穿透率分析、 UPS分析與C-V量測,分別得到能隙E_g=2.48 eV、功函數ϕ=3.95 eV與相對介電係數ϵ_(r(AZON))=12.8等特性參數。
第三部分旨在以具有高移動率與穩定性之最適化通道層薄膜Al(11.1%)-ZnON進行具CSE之元件的製作、量測與分析,並加以驗證模擬的設計與結果。在通道層增厚的實驗中未採用CSE之下閘極的結果顯示,通道厚度由20 nm增加至為40 nm時,導通電流、場效移動率與通道阻抗分別獲得了12.2倍的提升、48.7%的增加與90.2%的改善。探討Schottky type的表面結構的功函數與寬度變化實驗,結果呈現具蕭基金屬Pt並採用W_x=5 μm及Floating的條件擁有最優秀的電性(電流開關比為〖1.03×10〗^8、場效移動率為43.9 cm^2/V∙s、subthreshold swing為113 mV/dec以及通道阻抗為8.8 kΩ )。此外,於探討MOS type CSE的結果表明,採用W_x=5 μm及V_bias=0 V條件能有效地利用與通道電位分布V_c (x)間電位差增加半導體電位V_s使空乏深度得以加深,並改善關閉電流抑制問題。最後以通道厚度最大化的實驗量化具CSE於導通電流的提升效益與關閉電流的抑制能力,實驗結果得到,具最佳空乏能力的Schottky type CSE之通道厚度增加至45 nm時,導通電流相比於無CSE厚度為20 nm之AZON TFT具有7.83倍的增幅,且此時電流開關比依然保有約7.33倍,顯示了CSE於改善TFT特性的實驗結果與模擬結果所顯示之趨勢相符,證實本論文於採用CSE於增進TFT性能之效益。
本實驗成功以共濺鍍技術實現具CSE之Al(11.1%)-ZnON TFT,經過模擬與實驗的分析,以Schottky type (蕭基金屬Pt、W_x=0.25L及Floating條件)最具優勢,並主要體現於電流開關比、場效移動率與通道阻抗等電性上,這表示具CSE之TFT能同時擁有高驅動能力與低關閉功耗,達成元件電性改善,將有助於未來顯示技術之應用以及電子產品性能之提升。
In this thesis, we aim at the use of co-sputtering technology to incorporate Al into ZnON layer to realize high stable Al-ZnON (abbreviated as AZON) thin film transistors (TFTs) with improved performance. In addition, the employment of channel surface engineering (CSE) to form a Schottky junction and MOS structure on the channel surface are proposed and demonstrated, which could extend the channel thickness to harvest high electron mobility and low channel resistance while still retain the benefit of full depletion. The measurement results of AZON characteristic exhibit that the carrier mobility, concentration, energy gap, work function, and relative permittivity are 84.1 cm^2/V∙s, 〖3.09×10〗^18 cm^(-3), 2.48 eV, 3.95 eV, and 12.8, respectively. Simulation results show that TFTs with Schottky type CSE using Pt (5.65 eV) and W_x=0.25L under floating condition could have the largest on/off current ratio (〖5.87×10〗^16) and the best subthreshold swing (78 mV/dec). Experimental results also reveal that the use of Pt and W_x=5 μm under floating condition has the best performances with the on/off current ratio of 1.03×10^8, field mobility of 43.9 cm^2/V∙s, subthreshold swing of 113 mV/dec, and channel resistance of 8.8 kΩ. With the CSE technology to create addition depletion region in the channel, it makes possible to increase channel thickness to get high on current without destroy the full depletion of channel in off-state.
利用通道表面工程改善氮氧化鋁鋅薄膜電晶體特性之研究 I
Improving Electrical Performance of AZON Thin-FilmTransistors with Channel Surface Engineering V
誌謝 XI
目錄 XII
表目錄 XV
圖目錄 XVII
第一章 緒論 1
1-1平面顯示器發展概況 1
1-2氧化鋅基通道材料演進概述 2
1-3氮氧化鋅基通道材料挑戰概述 6
1-4通道表面工程簡介 10
1-5研究動機與架構 12
第二章 基礎理論建構 15
2-1 AZON簡化能帶圖及參數萃取方法 15
2-1-1 能帶理論概述 15
2-1-2 能隙參數萃取方法 17
2-1-3 能階參數萃取方法 18
2-1-4 簡化能帶圖投影法 20
2-2薄膜電晶體操作原理及通道薄化機制 22
2-2-1直流(靜止)電性操作 23
2-2-2 通道表面工程薄化機制 29
2-3薄膜電晶體參數及其萃取方法 37
第三章 元件結構模擬 44
3-1元件結構模擬規劃 44
3-2模擬工具及物理模型 45
3-3傳統下閘極TFT元件模擬 46
3-4 CSE之具Schottky結構TFT元件模擬 50
3-4-1 CSE空乏位置對元件特性之影響 50
3-4-2 Floating Case特性分析 51
3-4-3 Grounded Case特性分析 55
3-5 CSE之具MOS結構TFT元件模擬 56
3-6 CSE之模擬結果延伸(最大化通道厚度) 61
第四章 通道層薄膜與元件製備 64
4-1實驗方法及儀器設備介紹 64
4-2通道層膜薄製備 66
4-2-1氮氧化鋅(ZnON)通道薄膜製備 66
4-2-2氮氧化鋁鋅(AZON)通道薄膜製備 67
4-3傳統下閘極結構元件製備 68
4-4具通道表面結構之下閘極元件製備 72
第五章 通道層薄膜之電性量測及材料分析 75
5-1薄膜品質分析(Hall Measurement & XPS Analysis) 75
5-2 薄膜晶向分析(XRD Analysis) 87
5-3 薄膜簡化能帶圖(UV-VIS Transmissivity & UPS Analysis) 88
5-4 薄膜相對介電常數(C-V Measurement) 93
第六章 元件電性量測與分析 95
6-1傳統下閘極TFT元件電性分析 95
6-2 CSE之具Schottky結構TFT元件電性分析 98
6-3 CSE之具MOS表面結構結構TFT元件電性分析 101
6-4 CSE之實驗結果延伸(最大化通道厚度) 105
第七章 結論與未來研究建議 107
結論 107
未來研究之建議 112
參考資料 114
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