(3.237.97.64) 您好!臺灣時間:2021/03/03 00:50
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:吳則緯
研究生(外文):Tse-WeiWu
論文名稱:全內建之低功耗低頻振盪器
論文名稱(外文):Fully Built-In Low-Power Low-Frequency Oscillator
指導教授:魏嘉玲
指導教授(外文):Chia-Ling Wei
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:75
中文關鍵詞:全內建低頻振盪器
外文關鍵詞:Low power consumptionLow frequency
相關次數:
  • 被引用被引用:0
  • 點閱點閱:37
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著生醫、物聯網等產業近期迅速發展,無線通訊的接收、運算和輸出等眾多功能都要集中於同一晶片上,當製程越來越進步且功能越來越豐富,功耗和裝置本身的大小越來越重要。為了降低總功耗,讓系統處在待機或深度休眠模式會是比較有效率的方法,於必要時再喚醒系統執行任務,因此本研究將利用虛擬電阻(Pseudo-resistor)降低充電電流,設計一個全內建、面積小的低功耗低頻振盪器。
本研究使用台灣積體電路公司(TSMC)提供之0.18μm 1P6M Mixed-signal Standard CMOS製程,晶片總面積為0.968×0.838mm^2,並採用DIP 28 S/B進行封裝,晶片有四個版本的低頻振盪器,包含偏壓電路、充放電電路和比較邏輯電路,且不需要off-chip被動元件,各版本面積分別為0.083mm^2、0.0098mm^2、0.046mm^2、0.053mm^2,四個版本post-sim皆可輸出1Hz的方波,但量測結果不佳,最低頻率只有350Hz左右。
Low power consumption is important to wireless communication system. To reduce the power consumption, we can make the system stay in sleep-mode, and send a signal to wake it up and back to operation-mode. This thesis propose a fully built-in, low power consumption, and low frequency oscillator which meets the requirements. The output frequency of all versions are designed at 1Hz, and three of them are tunable frequency.
The proposed chip is fabricated by TSMC 0.18μm 1P6M mixed-signal standard CMOS process, and the chip area is 0.811 mm2. This chip includes four versions of low-frequency oscillator. The oscillator consists of three parts: bias circuit, charging-discharging circuit, and comparison logic circuit. Each version’s core area is 0.083mm^2, 0.0098mm^2, 0.046mm^2, and 0.053mm^2. The off-chip passive components are needless. The output frequency of all versions are 1Hz in the post-simulation. But the measurement result isn’t good, the lowest frequency is stable at around 355Hz under the same conditions.
第1章 簡介 1
1.1 研究動機 1
1.2 論文架構 2
第2章 文獻探討 3
2.1 背景知識 3
2.2 弛張振盪器研究近況 4
第3章 系統架構與電路設計 10
3.1 系統架構簡介 10
3.2 電路設計與功能介紹 10
3.2.1 全系統Version 1 10
3.2.2 全系統Version 2 20
3.2.3 全系統Version 3 27
3.2.4 全系統Version 4 28
第4章 模擬結果與佈局考量 30
4.1 模擬結果 30
4.1.1 子電路模擬 30
4.1.2 全系統模擬 32
4.2 佈局考量 41
4.3 打線圖 43
第5章 量測結果 45
5.1 量測環境與考量 45
5.2 量測結果與討論 47
5.3 規格與效能比較表 56
第6章 結論與未來展望 58
參考文獻 59
[1] D. Djekic, M. Ortmanns, G. Fantner, and J. Anders, “A tunable, robust pseudo-resistor with enhanced linearity for scanning ion-conductance microscopy, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, pp. 842–845.
[2] D. Djekic, G. Fantner, J. Behrends, K. Lips, M. Ortmanns, and J. Anders, “A transimpedance amplifier using a widely tunable PVT-independent pseudo-resistor for high-performance current sensing applications, in Proc. 43rd IEEE Eur. Solid State Circuits Conf. (ESSCIRC), Sep. 2017, pp. 79–82.
[3] D. Djekic, G. Fantner, J. Behrends, K. Lips, M. Ortmanns, and J. Anders, “A 0.1% THD, 1-MΩ to 1-GΩ Tunable, Temperature-Compensated Transimpedance Amplifier Using a Multi-Element Pseudo-Resistor, in IEEE J. Solid-State Circuits, vol. 53, no. 7, July 2018.
[4] S. Zhang, X. Zhou and Q. Li, “A Voltage Swing Robust Pseudo-Resistor Structure for Biomedical Front-end Amplifier, in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, pp. 61–64.
[5] A. Tajalli, Y. Leblebici, and E. Brauer, “Implementing ultra-high-value floating tunable cmos resistors, Electronics Letters, vol. 44, no. 5, pp. 349–350, Feb 2008.
[6] Y. W. Wang, “A Wide-Range Programmable Sinusoidal Frequency Synthesizer for Electrochemical Impedance Spectroscopy Measurement System, M.S. thesis, Dept. of Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R.O.C., July 2012.
[7] D. Ruffieux, F. Krummenacher, A. Pezous, and G. Spinola-Durante, “Silicon resonator based 3.2 μW real time clock with ±10 ppm frequency accuracy, in IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 224–234, Jan. 2010.
[8] J. Lim, K. Lee, and K. Cho, “Ultra low power RC oscillator for system wake-up using highly precise auto-calibration technique, in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2010, pp. 274–277.
[9] K.J. Hsiao, “A 32.4 ppm/ C 3.2–1.6 V self-chopped relaxation oscillator with adaptvie supply generation, in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2012, pp. 14–15.
[10] S. Jeong, I. Lee, D. Blaauw, and D. Sylvester, “A 5.8 nW, 45 ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme, in Proc. IEEE Custom Integr. Circuits Conf. (CICC), 2014, pp. 1–4.
[11] J. J. Jhang, “Fully-Integrated Boost DC-DC Converter with Low-Startup Voltage for Thermoelectric Harvester, M.S. thesis, Dept. of Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R.O.C., June 2018.
[12] Y. Ni and M. Onabajo, “A low-power temperature-compensated CMOS relaxation oscillator, in Analog Integrated Circuits and Signal Processing, vol. 79, pp. 309–317, May 2014.
[13] U. Denier, “Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator, in IEEE Transactions on Circuits and Systems I, vol. 57, no. 8, pp. 1973-1982, Aug. 2010
[14] B. Cimbili, D. Wang, R.C. Zhang, X.L. Tan, P.K. Chan, “A PVT-Tolerant Relaxation Oscillator in 65nm CMOS, in IEEE Region 10 Conference (TENCON), 2016, pp.2315-2318.
[15] V. Delport, “Low Power Wireless Sensor Networks.
Reference: (https://www.digikey.be/nl/articles/techzone/2011/may/low-power-wireless-sensor-networks)
[16] A. Paidimarri, D. Griffith, A. Wang, A. Chandrakasan, and G. Burra, “A 120 nW 18.5 kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability, in IEEE ISSCC Dig. Tech. Papers, 2013, pp. 184–185.
[17] A. Paidimarri, D. Griffith, A. Wang, G. Burra, and A. P. Chandrakasan, “An RC oscillator with comparator offset cancellation, in IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1866–1877, Aug. 2016.
[18] K. Tsubaki, T. Hirose, N. Kuroki, and M. Numa, “A 32.55 kHz, 472nW, 120 ppm/◦C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application, in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), 2013, pp. 315–318.
[19] J. Jung, I.-H. Kim, S.-J. Kim, Y. Lee, and J.-H. Chun, “A 1.08-nW/kHz 13.2-ppm/◦C self-biased timer using temperature-insensitive resistive current, in IEEE J. Solid-State Circuits, vol. 53, no. 8, pp. 2311–2318, Aug. 2018.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關論文
 
無相關期刊
 
無相關點閱論文
 
系統版面圖檔 系統版面圖檔