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研究生:張煒義
研究生(外文):Wei-YiChang
論文名稱:採用超參數優化技術來降低三維晶片溫度且以矽穿孔為導向之平面規劃方法
論文名稱(外文):TSV-driven Floorplanning using Hyperparameter Optimization Technique to Minimize Temperature in 3D ICs
指導教授:林家民林家民引用關係
指導教授(外文):Jai-Ming Lin
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:108
語文別:英文
論文頁數:51
中文關鍵詞:平面規劃三維晶片矽穿孔固定框架溫度
外文關鍵詞:floorplanning3D-ICTSVfixed-outlinetemperature
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三維晶片(Three-dimensional Integrated Circuit, 3D IC)被認為是能夠延續摩爾定律的關鍵技術,其結構是以數層晶粒(die)沿垂直方向堆疊而成,並利用矽穿孔(Through Silicon Vias, TSVs)作為不同晶粒之間傳輸訊號的路徑,此架構不僅能提升晶片整體效能,亦可實現異質整合。然而,將晶粒垂直堆疊後將會使垂直方向的功率密度提高,晶粒之間絕緣層的低導熱性也使得散熱不易,致使晶片溫度顯著上升。為了避免高溫造成晶片性能或可靠度下降,熱效應是三維晶片在實體設計階段不可忽視的議題之一。
過往針對熱效應的三維平面規劃演算法,多半採用模擬退火法,但此方法通常導致不穩定的結果及過長的執行時間。除此之外,矽穿孔的良好導熱性使之成為晶粒間傳輸熱的主要路徑,過去的方法在考慮此項影響時,卻無法估算矽穿孔的溫度影響並進行優化,而層與層之間堆疊結構造成的溫度影響也沒有詳細探討。鑒於以上原因,本論文提出考慮線長及固定框架限制,同時優化溫度的三維平面規劃方法,此方法可略分為四個階段: (1)模塊分層階段:大略估測各層溫度結果並分配模塊至各層晶粒 (2)全域散佈階段:將溫度平均散佈至晶片各處 (3)合法化階段:不過份影響散佈結果下,逐層得出不違反固定框架限制的平面規劃結果 (4)矽穿孔指派階段:逐層決定各矽穿孔確切的位置,進一步優化繞線長度(wirelength)以及溫度。
High temperature or temperature non-uniformity has become a serious threat to performance and reliability of high performance integrated circuits (ICs). Thermal effect becomes a non-ignorable issue to circuit design or physical design. In 3D ICs, this issue becomes more severe than in 2D ICs due to the high integrated densities and the difficulties in heat transfer. The temperature in 3D ICs can be significantly affected by the locations of modules and TSVs. Hence, it is important to develop an efficient and effective 3D thermal-aware floorplanner.
This paper adopts a tier assignment method to assign modules to tiers while considering the power distribution between tiers and the number of TSVs. To determine the location of each module, we apply a thermal-aware floorplanning methodology that can consider the wirelength and the temperature at the same time under the fixed-outline constraint. Finally, we determine the locations of TSVs to construct a better heat transfer path without inducing longer wirelength. Experimental results have demonstrated that the proposed methodology can significantly reduce the temperature in 3D ICs with slight increase in wirelength. More importantly, our runtime is quite fast.
摘要 1
Abstract 2
誌謝 3
Table of Contents 4
List of Tables 6
List of Figures 7
Chapter 1 Introduction 8
1.1 Previous Works 10
1.1.1 Temperature Analysis Approach 10
1.1.2 3D Floorplanning Considering Thermal Issue 11
1.1.3 Methodologies considering TSVs Issues 11
1.2 Our Contributions 13
1.3 Thesis Organization 14
Chapter 2 Problem Formulation 15
Chapter 3 Preliminaries 16
3.1 Wirelength Estimation 16
3.2 Thermal-aware Floorplanning Methodology [16] 18
3.2.1 Global Distribution Stage 18
3.2.2 Local Legalization Stage 20
Chapter 4 3D Thermal-aware Floorplanning Algorithm 22
4.1 Overview of Our Methodology. 22
4.2 Numerical Method for Temperature Analysis 23
4.2.1 Simplified Electro-Thermal Model 23
4.2.2 Temperature Analysis by Node Based Method 24
4.3 Power Density-aware Tier Assignment 26
4.3.1 Power Density-aware Tier Assignment Algorithm 26
4.3.2 Search for Target Power Density Combination 29
4.3.3 Power Density-aware F-M Based Algorithm 29
4.4 3D Thermal-aware Global Distribution Stage 31
4.4.1 Analytical Formulation 32
4.4.2 Sub-3D Thermal Mask to Approximate Temperature 32
4.4.3 Thermal-aware Clustering 33
4.5 Thermal-aware TSV Assignment Stage 35
4.5.1 Power Variation Estimation 35
4.5.2 Min-Cost-Max-Flow TSV Assignment 36
Chapter 5 Experimental Results 39
5.1 Effect of Power-Density Aware Tier Assignment 40
5.2 Effect of Thermal-aware TSV Assignment 43
5.3 Comparison with Corblivar [12] 45
Chapter 6 Conclusion 48
Bibliography 49
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