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[1] T. W. Williams, R. Kapur, M. R. Mercer, R. H. Dennard, and W. Maly, “Iddq testing for high performance CMOS - the next ten years,” in Proc. of European Design and Test Conference (EDTC), pp. 578-583, March 1996. [2] S. S. Sabade and D. M. Walker, “IDDX-based test methods: a survey,” ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 9, no. 2, pp. 159-198, April 2004. [3] T. A. Unni and D. M. H. Walker, “Model-based IDDQ pass/fail limit setting,” in Proc. of IEEE Int'l Workshop on IDDQ Testing, pp. 43-47, Nov. 1998. [4] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” in Proc. of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003. [5] S. S. Sabade and D. H. M. Walker, “Use of multiple IDDQ test metrics for outlier iden-tification,” in Proc. of VLSI Test Symp. (VTS), pp. 31-38, May 2003. [6] A. E. Gattiker and W. Maly, “Current signatures [VLSI circuit testing],” in Proc. of VLSI Test Symp. (VTS), pp. 112-117, April 1996. [7] T. J. Powell, J. Pair, M. St. John, and D. Counce, “Delta IDDQ for testing reliability,” in Proc. of VLSI Test Symp. (VTS), pp. 439-443, Aug. 2000. [8] P. Engelke, I. Polian, H. Manhaeve, M. Renovell, and B. Becker, “Delta-IDDQ testing of resistive short defects,” in Proc. of Asian Test Symp. (ATS), pp. 63-68, Nov. 2006. [9] W. R. Daasch, J. McNames, D. Bockelman, and K. Cota, “Variance reduction using wafer patterns in IddQ data,” in Proc. of Int'l Test Conf. (ITC), pp. 189-198, Oct. 2000. [10] W. R. Daasch, K. Cota, J. McNames, and R. Madge, “Neighbor selection for variance reduction in IDDQ and other parametric data,” in Proc. of Int'l Test Conf. (ITC), pp. 1240-1248, Oct. 2001. [11] S. S. Sabade and D. M. H. Walker, “Improved wafer-level spatial analysis for IDDQ limit setting,” in Proc. of Int'l Test Conf. (ITC), pp. 82-91, Nov. 2001. [12] C.-L. L. Chang and C. H.-P. Wen, “Demystifying Iddq data with process variation for automatic chip classification,” IEEE Trans. on Very Large Scale Integration (VLSI) Sys-tems (TVLSI), vol. 23, no. 6, pp. 1175-1179, June 2015. [13] D. Shaw, D. Hoops, K. M. Butler, and A. Nahar, “Statistical outlier screening as a test solution health monitor,” in Proc. of Int'l Test Conf. (ITC), pp. 1-10, Nov. 2016. [14] A. Nahar et al., “Quality improvement and cost reduction using statistical outlier meth-ods,” in Proc. of Int'l Conf. on Computer Design (ICCD), pp. 64-69, Oct. 2009. [15] R. Turakhia, B. Benware, R. Madge, T. Shannon, and R. Daasch, “Defect screening using independent component analysis on IDDQ,” in Proc. of VLSI Test Symp. (VTS), pp. 427-432, May 2005. [16] N. Sumikawa, J. Tikkanen, L.-C. Wang, L. Winemberg, and M. S. Abadir, “Screening customer returns with multivariate test analysis,” in Proc. of Int'l Test Conf. (ITC), pp. 1-10, Nov. 2012. [17] H. C. M. Bossers, J. L. Hurink, and G. J. M. Smit, “Selection of tests for outlier detec-tion,” in Proc. of VLSI Test Symp. (VTS), pp. 1-6, April 2013. [18] T. Haifley et al., “Guidelines for part average testing,” Automotive Electronics Council, pp. 1-9, Dec. 2011. [19] J. R. Gardner et al., “GPyTorch: blackbox matrix-matrix Gaussian process inference with GPU acceleration,” Proc. of Int'l Conf. on Neural Information Processing Systems (NeurIPS), pp. 7587-7597, Dec. 2018.
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