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研究生:陳均騰
研究生(外文):Chen, Chun-Teng
論文名稱:基於卷積神經網路架構生成隨機回歸模型之穩態電流偵測流程
論文名稱(外文):CNN-based Stochastic Regression for IDDQ Outlier Identification
指導教授:吳凱強
口試委員:趙家佐陳瑩晏
口試日期:2019-11-27
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊科學與工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:108
語文別:英文
論文頁數:23
中文關鍵詞:異常值偵測卷積神經網路隨機回歸模型空間關聯穩態電流
外文關鍵詞:outlier identificationCNNstochastic regressionspatial correlationiddq
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  • 被引用被引用:0
  • 點閱點閱:286
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摘要 i
Abstract ii
Acknowledgements iii
Chapter 1 Introduction 1
Chapter 2 Motivation 4
2.1 Example 1 4
2.2 Example 2 5
2.3 Example 3 5
2.4 Paper Contribution 6
Chapter 3 Proposed Methodology 8
3.1 Problem Statement 8
3.2 CNN Encoding 10
3.3 CNN Architecture 12
Chapter 4 Experimental Results 16
4.1 Results of CNN-based Stochastic Regression 17
4.2 Comparison against Different Input Channels 19
4.3 Results with various IDDQ patterns 19
4.4 Discussion on Inference Time 20
Chapter 5 Conclusion 21
Bibliography 22
[1] T. W. Williams, R. Kapur, M. R. Mercer, R. H. Dennard, and W. Maly, “Iddq testing for high performance CMOS - the next ten years,” in Proc. of European Design and Test Conference (EDTC), pp. 578-583, March 1996.
[2] S. S. Sabade and D. M. Walker, “IDDX-based test methods: a survey,” ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 9, no. 2, pp. 159-198, April 2004.
[3] T. A. Unni and D. M. H. Walker, “Model-based IDDQ pass/fail limit setting,” in Proc. of IEEE Int'l Workshop on IDDQ Testing, pp. 43-47, Nov. 1998.
[4] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” in Proc. of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
[5] S. S. Sabade and D. H. M. Walker, “Use of multiple IDDQ test metrics for outlier iden-tification,” in Proc. of VLSI Test Symp. (VTS), pp. 31-38, May 2003.
[6] A. E. Gattiker and W. Maly, “Current signatures [VLSI circuit testing],” in Proc. of VLSI Test Symp. (VTS), pp. 112-117, April 1996.
[7] T. J. Powell, J. Pair, M. St. John, and D. Counce, “Delta IDDQ for testing reliability,” in Proc. of VLSI Test Symp. (VTS), pp. 439-443, Aug. 2000.
[8] P. Engelke, I. Polian, H. Manhaeve, M. Renovell, and B. Becker, “Delta-IDDQ testing of resistive short defects,” in Proc. of Asian Test Symp. (ATS), pp. 63-68, Nov. 2006.
[9] W. R. Daasch, J. McNames, D. Bockelman, and K. Cota, “Variance reduction using wafer patterns in IddQ data,” in Proc. of Int'l Test Conf. (ITC), pp. 189-198, Oct. 2000.
[10] W. R. Daasch, K. Cota, J. McNames, and R. Madge, “Neighbor selection for variance reduction in IDDQ and other parametric data,” in Proc. of Int'l Test Conf. (ITC), pp. 1240-1248, Oct. 2001.
[11] S. S. Sabade and D. M. H. Walker, “Improved wafer-level spatial analysis for IDDQ limit setting,” in Proc. of Int'l Test Conf. (ITC), pp. 82-91, Nov. 2001.
[12] C.-L. L. Chang and C. H.-P. Wen, “Demystifying Iddq data with process variation for automatic chip classification,” IEEE Trans. on Very Large Scale Integration (VLSI) Sys-tems (TVLSI), vol. 23, no. 6, pp. 1175-1179, June 2015.
[13] D. Shaw, D. Hoops, K. M. Butler, and A. Nahar, “Statistical outlier screening as a test solution health monitor,” in Proc. of Int'l Test Conf. (ITC), pp. 1-10, Nov. 2016.
[14] A. Nahar et al., “Quality improvement and cost reduction using statistical outlier meth-ods,” in Proc. of Int'l Conf. on Computer Design (ICCD), pp. 64-69, Oct. 2009.
[15] R. Turakhia, B. Benware, R. Madge, T. Shannon, and R. Daasch, “Defect screening using independent component analysis on IDDQ,” in Proc. of VLSI Test Symp. (VTS), pp. 427-432, May 2005.
[16] N. Sumikawa, J. Tikkanen, L.-C. Wang, L. Winemberg, and M. S. Abadir, “Screening customer returns with multivariate test analysis,” in Proc. of Int'l Test Conf. (ITC), pp. 1-10, Nov. 2012.
[17] H. C. M. Bossers, J. L. Hurink, and G. J. M. Smit, “Selection of tests for outlier detec-tion,” in Proc. of VLSI Test Symp. (VTS), pp. 1-6, April 2013.
[18] T. Haifley et al., “Guidelines for part average testing,” Automotive Electronics Council, pp. 1-9, Dec. 2011.
[19] J. R. Gardner et al., “GPyTorch: blackbox matrix-matrix Gaussian process inference with GPU acceleration,” Proc. of Int'l Conf. on Neural Information Processing Systems (NeurIPS), pp. 7587-7597, Dec. 2018.
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