臺灣博碩士論文加值系統

本論文分為兩個部分，其中之一為低功耗高速隨機存取記憶體設計。本論文提出新的5T 記憶體細胞搭配多組暫態調變的電壓源，並採用緊密的細胞陣列和開放式字元線架構，以達到略小於記憶體編譯器的核心面積大小。於靜態和讀寫操作時，透過輔助電路和暫態調變電壓源來分別優化速度、功耗和讀寫可靠性。並透過局部追蹤電路的設計，確保控制信號在製程、電壓和溫度的漂移下仍擁有正確的操作時間。於28奈米的CMOS製程下，量測結果顯示出正確的讀寫功能且透過進一步的電路修正，模擬結果可達到次奈秒讀寫及次毫瓦每千兆赫茲。
本論文第二部份為記憶體內運算的多位元緩衝器設計，由於靜態隨機存取記憶體細胞只有單位元的存取能力，因此我們透過安排儲存位元的方式並設計多位元緩衝器，以此提出輸入、參數和輸出皆可選擇的可重組式記憶體運算內架構。多位元緩衝器採用雙級轉導放大器形成的閉迴路單位增益緩衝器。於28奈米的CMOS製程下，模擬結果證明此架構可於製程、電壓和溫度飄移下，仍維持正確的功能。

This thesis has two portions, one is low power and high speed SRAM design. In this design, we propose a new 5T SRAM cells with multiple power supply voltages pulsed. Besides, we apply compact array architecture and open-BL to have smaller core area as compared to memory compiler. In idle, read or write mode, using assistant circuits and adaptive supply voltages of cells to optimize speed, power and reliability, respectively. Moreover, the design of tracking circuit is to ensure control correctness within PVT variation. In 28nm CMOS technology, the measurement results show the correct function. After the enhanced key modules design, the simulation results show the performance of sub-ns access with sub-mW/GHz.
The second portion of this thesis is designs of multi-bit buffer in In-Memory Computing. Because SRAM cells can just store single bit data, we arrange the storing order of data and have multi-bit buffers to propose the reconfigurable architecture. This architecture can provide optional bit number of input, weigh and output. In buffer designs, we apply Two stage OTA to form a closed loop unity-gain buffer. In 28nm CMOS technology, simulation results show the function correctness within PVT variation.

Chapter 1 Introduction 1
1.1 Motivation and Goals 1
1.2 Thesis Organization 2
Chapter 2 Overview of Embedded SRAM Design 3
2.1 The Architecture of SRAM array 3
2.1.1 Non-Bit-Interleaving Architecture 4
2.1.2 Bit-Interleaving Architecture 5
2.1.3 Hierarchy Bit-Line and Ripple Bit-Line 6
2.1.4 Large Signal and Differential Signal Sensing Scheme 8
2.1.5 Pipelined Design 11
2.2 The Overview of SRAM Assistant Circuits 12
2.2.1 Adaptive Supply Voltage of Cells 12
2.2.2 Boost Word-Line Voltage 13
2.2.3 Two Step Word-Line Voltage 14
2.2.4 Double Metal Word-Line 15
2.2.5 Bit-Line Under Drive 16
2.2.6 Negative Write Bit-Line 17
2.3 Summary 18
Chapter 3 Sub-0.5V Low Power and High Speed 32Kb 5T SRAM Design 19
3.1 Functional Block of the Proposed 5T SRAM 20
3.1.1 The Operation Scheme of 5T SRAM Cells 20
3.1.2 The Array Architecture of 5T SRAM 25
3.2 The Design of 5T SRAM Peripheral Circuits 30
3.2.1 Slow Boosted Word-Line Voltage 30
3.2.2 Short Bit-Line and Delayed Hierarchical Switch 34
3.2.3 Adaptive Read Write Power Supply for 5T SRAM Cells 38
3.2.4 Replica Circuits for Tracking and Control 46
3.3 Measurement Results of Chip 1 and Simulation Results of Chip 2 49
3.3.1 Measurement Results of Chip 1 49
3.3.2 Simulation Results of Chip 2 50
3.4 Summary 52
Chapter 4 Designs of Multi-Bit Buffer for ADC Input Stage in A Reconfigurable In-Memory Computing Architecture 53
4.1 The Overview of In-Memory Computing (IMC) 53
4.1.1 Multiply and Accumulation (MAC) and IMC 53
4.1.2 Column-Based and Row-Based MAC with IMC 55
4.1.3 Multi-Bit MAC with IMC 58
4.2 The Proposed Reconfigurable IMC Architecture 61
4.2.1 The Design Concept of Reconfigurable IMC Architecture 61
4.2.2 The Operation Scheme of ADC Input Buffer 63
4.3 The Design of Multi-Bit Buffer for ADC Input Stage 65
4.3.1 Specification 65
4.3.2 Circuit Design 66
4.4 Simulation Results 71
4.4.1 Floor Plan and Layout 71
4.4.2 Post-Layout Simulations 73
4.5 Summary 77
Chapter 5 Conclusions 78
Reference 80

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