臺灣博碩士論文加值系統

「人工智慧(AI)」早期主要是指機器可以根據外界刺激訊號自動化地給予反應與回饋，然而，隨著物聯網的普及人工智慧的範疇也因為不同的需求而有了不同的定義。其中以貼近生活的智能運動手錶、智能喇叭等邊緣裝置的需求更是與日俱增。由於邊緣裝置必須根據周邊環境的變化在短時間內快速且精準地回傳指令及動作，因此人工智慧除了要能提供資訊回饋，更要能以低能耗高效能的方式進行數據計算。
當今的人工智慧雖然可以利用演算法高效率地處理數據，但其運算是建立在傳統范紐曼 (von Neumann) 計算架構之上，故對於邊緣裝置資訊傳輸上所產生的延遲時間與相對能耗問題仍難有所突破。在眾多的計算架構改善方案中，以模仿人類大腦神經網絡與演算法之仿生運算系統最受矚目。仿生運算系統將計算與儲存數據同時在單一電子元件中進行，而其中關鍵的類突觸電子元件需具備高密度排列、三維堆疊、低能耗、短操作時間且同時具備突觸可塑性等特性，一直是目前仿生運算架構的最大瓶頸。
前瞻性的鐵電式穿隧記憶體利用本身材料的特性及物理機制，相對於當今廣泛研究的電阻式記憶體、磁阻式記憶體擁有更穩定的可靠度及更低能耗。本論文有系統地探討從鐵電穿隧式記憶元件的結構與製程設計，及其在未來邊緣裝置應用的必要性。
由於鐵電穿隧式記憶體的記憶單元機制不同於鐵電電容式記憶體及鐵電電晶體，在本論文初期我們先針對電極的金屬選擇對於元件電偶極矩、記憶窗口大小、耐久性可靠度做評估；除了記憶窗口大小外，在過去鐵電穿隧式記憶體的研究中，對於元件電流大小與電偶極矩方向之間的關係尚未有共識，因此我們建立了物理模擬模型以釐清鐵電薄膜層與介面氧化層的關係，並提供未來元件設計的指南；基於鐵電穿隧式記憶體做為二元類神經突觸的可行性及奈安培等級的低電流特性，我們也分析了此類低電流元件於二元神經網絡硬體應用的潛力。
本文之貢獻在於成功製備出一個能在50奈秒快速寫入、長達一千萬次的耐久性與十年記憶能力的高可靠度穿隧式記憶體。除了元件的製備與特性分析，本文也在模擬結果下給予未來元件優化的方向，如可藉由介面層材料與未製的調整控制整體電流趨勢。我們展現此低能耗且快速操作的元件在邊緣裝置的應用，可以在不影響推論高達86.4%精準度的情形提供更高效能且快速的計算與反饋。

People imagine a better world where devices, machines, things are more intelligent, ubiquitous, and enriching our lives. Among all applications of the internet of things (IoTs), the devices which are close to our daily lives are called edge devices. These edge devices are required to response commands and actions within a limited time when they were triggered. In addition to returning feedback rapidly, edge devices must be able to process data with low power consumption.
However, artificial intelligence (AI) based on the traditional von Neumann architectures computes data in a time- and power-consuming way, because the data storage units and arithmetic units are separated physically. On the other hand, in the neuromorphic computing system, the data can be stored and computed in a single electronic synaptic device. The critical synaptic device should satisfy the strict requirements of high-density, 3D-stackable, low-energy consumption, high-speed operating, and perfect synaptic plasticity, thus remaining as the major bottleneck in the development of neuromorphic computing systems.
Until now, the applications of resistive-switching memory (RRAM) and magnetoresistive memory (MRAM) on neuromorphic computing have been widely studied. Compared to the actively researched RRAM and MRAM, the emerging ferroelectric tunnel junction memory (FTJ) provides more robust reliability and lower power consumption. This thesis systematically discusses the FTJ design and its necessity for edge devices.
Because the cell structure and operation of FTJ is different from that of FeRAM and FeFET, we first discussed the dependence of FTJ characteristics on the polarization density and electrode materials. Moreover, the relation between the tunneling current switching and the dipole direction proposed from other groups often contradict to each other and remains controversial. Hence, we built a physical simulation model to clarify the device operating mechanism. Afterward, by comparing different oxide stacks in FTJ devices, we provided a guideline for improving FTJ designs. Because of numerous attractive properties, FTJ shows immense potential as a binary synaptic device. Finally, we also analyzed the potential of such low-current memory cells in binary neural network hardware applications.
In conclusion, we successfully demonstrated a sub-nA low-current, 50ns high-speed, 107 endurance, and ten years retention high-reliability FTJ. We demonstrate with sub-nA memory cell in-memory computing can achieve better accuracy and remarkable 702, 101, and 7×104 times improvements in power, area, and energy-area product efficiency. Furthermore, we not only discussed the fabrication and characteristics of this emerging device but also provided useful guidelines for future optimization. For instance, we can control the switching I-V and related MW by inserting different interfacial layers in a different position.

摘要 i
Abstract iii
Acknowledgment v
Contents vii
Figure Captions x
Table List xiv
Chapter 1 Introduction 1
1.1 Towards an AI-Driven World 1
1.2 In-Memory Computing 2
1.3 Non-Filamentary RRAM 3
1.3.1. Switching mechanism 4
1.3.2. XAS analysis 5
1.3.3. Limitation 9
1.4 Filamentary RRAM 10
1.4.1 Switching mechanism 10
1.4.2 Limitation 11
1.4.3 Operation optimization 12
1.5 Ferroelectric Memory 14
1.5.1 Ferroelectric material 14
1.5.2 FeRAM 16
1.5.3 FeFET 16
1.5.4 FTJ 16
1.6 Motivation 17
Chapter 2 Ferroelectric Tunnel Junction 19
2.1 Introduction 19
2.2 Wake-up and fatigue effect 22
2.3 Device fabrication 25
2.4 Results and discussion 25
2.4.1 Measurement setup 25
2.4.2 Measurement flow 29
2.4.3 Characteristic comparison 30
2.5 Physical analysis 32
2.6 Summary and conclusion 34
Chapter 3 FTJ DC tunneling current 36
3.1 Introduction 36
3.2 DC I-V characteristic 37
3.3 Simulation 40
3.4 Results and discussion 43
3.4.1 Device fabrication 43
3.4.2 Switching mode comparison 44
3.4.3 Tunneling memory window comparison 48
3.4.4 Insertion position comparison 50
3.5 Summary and conclusion 52
Chapter 4 FTJ synaptic device on low power AI hardware 54
4.1 Introduction 54
4.2 Device reliability 55
4.3 Multi-level-cell possibility 57
4.4 IMC based on low-current FTJ 61
4.4.1 Convolutional neural networks with IMC 61
4.4.2 Array scheme 64
4.4.3 Simulation results 67
4.5 Summary 69
Chapter 5 Conclusion and future work 70
5.1 Conclusion 70
5.2 Future work 71
Reference 72
Vita 77

[1] openai [online] Available: https://openai.com/blog/ai-and-compute/
[2] S. Yu, “Neuro-inspired computing with emerging nonvolatile memory,” Proc. IEEE, vol. 106, no. 2, pp. 260-285, Feb. 2018.
[3] Wikipedia, “Human brain” [Online]. Available: https://en.wikipedia.org/wiki/Human_brain.
[4] M. Kim, P. Smaragdis, “Bitwise Neural Networks,”arXiv:1601.06071v1, 2016.
[5] M. Rastegari, V. Ordonez, J. Redmon, A. Farhadi., “XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks,” arXiv:1603.05279v4, 2016.
[6] M. Courbariaux, Y. Bengio, and J-P David, “BinaryConnect: Training Deep Neural Networks with binary weights during propagations,” arXiv:1511.00363, 2015.
[7] F. Pan, S. Gao, C. Chen, C. Song, F. Zeng, “Recent progress in resistive random access memories: materials switching mechanisms and performance,” Materials Science and Engineering: R: Reports, vol. 83, pp. 1-59, 2014.
[8] T.-C. Chang, K.-C. Chang, T.-M. Tsai, T.-J. Chu, S. M. Sze, “Resistance random access memory” Mater. Today, vol. 19, no. 5, pp. 254-264, Jun. 2016.
[9] C.-C. Chang, P.-C. Chen, B. Hudec, P. –T. Liu, T.-H. Hou, “Interchangeable Hebbian and Anti-Hebbian STDP Applied to Supervised Learning in Spiking Neural Network,” in IEDM Tech. Dig., pp. 15.5.1-15.5.4., Dec. 2018.
[10] Wikipedia, “X-ray absorption spectroscopy” [Online]. Available: https://en.wikipedia.org/wiki/X-ray_absorption_spectroscopy.
[11] NSRRC course lecture.
[12] I.-T. Wang, Y.-C. Lin, Y.-F. Wang, C.-W. Hsu and T.-H. Hou, “3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation,” in IEDM Tech. Dig., pp. 28.5.1-28.5.4, Dec. 2014.
[13] G. H. Buh, I. Hwang, B.-H. Park, “Time-dependent electroforming in NiO resistive switching devices,” Appl. Phys. Lett., vol. 95, 142101, Oct. 2009.
[14] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita, S. Spiga, C. Wiemer, M. Perego, M. Panciulli, “Conductive-filament switching analysis and self-accelerated thermal dissolution model for reset in NiO-based RRAM,” in IEDM Tech. Dig., pp. 775–778, 2007.
[15] B. Gao, S. Yu, N. Xu, L.-F. Liu, B. Sun, X.-Y. Liu, R.-Q. Han, J.-F. Kang, B. Yu, Y.-Y. Wang, “Oxide-based RRAM switching mechanism: A new ion-transport-recombination model,” in IEDM Tech. Dig., 2008, pp. 563–566.
[16] S. Yu and H.-S. P. Wong, “A phenomenological model for the reset mechanism of metal oxide RRAM,” IEEE Electron Device Lett., vol. 31, no. 12, pp. 1455–1457, 2010.
[17] W.-C. Luo, J.-C. Liu, H.-T. Feng, Y.-C. Lin, J.-J. Huang, K.-L. Lin and T.-H. Hou, “RRAM set speed-disturb dilemma and rapid statistical prediction methodology,” in IEDM Tech. Dig., 2012, pp. 215–218.
[18] W.-C. Luo, J.-C. Liu, Y.-C. Lin, C.-L. Lo, J.-J. Huang, K.-L. Lin and T.-H. Hou, “Statistical model and rapid prediction of RRAM SET speed-disturb dilemma,” IEEE Trans. Electron Devices, vol. 60, pp. 3760–3766, 2013.
[19] J.-C. Liu, T.-Y. Wu, T.-H. Hou, “Optimizing incremental step pulse programming for RRAM through device–circuit co-design,” IEEE Trans Circuits Syst II, 65, 617–621,2018.
[20] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, U. Böttger, “Ferroelectricity in hafnium oxide thin films,” Appl. Phys. Lett., 99, 102903, 2011.
[21] T. Shimada, T. Kitamura, “Multi‐physics properties in ferroelectric nanowires and related structures from first‐principles,” in Nanowires, P. Prete Eds., Croatia: INTECH, 2010.
[22] C. Liu, F. Liu, Q. Luo, P. Huang, X.-X. Xu, H.-B. Lv, Y.-D. Zhao, X.-Y. Liu and J.-F. Kang, “Role of Oxygen Vacancies in Electric Field Cycling Behaviors of Ferroelectric Hafnium Oxide,” in IEDM Tech. Dig., pp.16.4.1-16.4.4, 2018.
[23] K. Takeuchi, A. Chen, “Ferroelectric FET Memory,” in Emerging Nanoelectronic Devices, A. Chen, J. Hutchby, V. Zhirnow, G. Bourianoff, Eds West Sussex: John Wiley and Sons Ltd, 2015, pp.111, 2015.
[24] T. Mikolajick, S. Slesazeck, M.-H. Park, U. Schroeder, “Ferroelectric hafnium oxide for ferroelectric random-access memories and ferroelectric field-effect transistors,” MRS Bull., vol. 43, no. 5, pp. 340-346, May 2018.
[25] S. Fujii, Y. Kamimuta, T. Ino, Y. Nakasaki, R. Takaishi, M. Saitoh, “First demonstration and performance improvement of ferroelectric HfO2-based resistive switch with low operation current and intrinsic diode property,” in Symp. VLSI Tech. Dig., 2016.
[26] J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick, L. Frey, “Ferroelectric Zr0.5Hf0.5O2 thin films for nonvolatile memory applications” Appl. Phys. Lett., 11, 112901, 2011.
[27] M.-H. Park, H.-J. Kim, Y.-J. Kim, T. Moon, C.-S. Hwang, “The effects of crystallographic orientation and strain of thin Hf0.5Zr0.5O2 film on its ferroelectricity,” Appl. Phys. Lett., 104, 072901, 2014.
[28] X. Zhang, L. Chen, Q.-Q. Sun, L.-H. Wang, P. Zhou, L. Hong, P.-F. Wang, S.-J. Ding, David W. Zhang, “Inductive crystallization effect of atomic-layer-deposited Hf0.5Zr0.5O2 films for ferroelectric application,” Nanoscale Res. Lett., 10, 25, 2015.
[29] Z. Fan, J. Xiao, J. Wang, L. Zhang, J. Deng, Z. Liu, Z Dong, J. Wang, and J. Chen, “Ferroelectricity and ferroelectric resistive switching in sputtered Hf0.5Zr0.5O2 thin films,” Appl. Phys. Lett., 108, 23, 232905, 2016.
[30] F. Ambriz-Vargas, G. Kolhatkar, R. Thomas, R. Nouar, A. Sarkissian, C. Gomez-Yáñez, M. A. Gauthier, and A. Ruedige, “Tunneling electroresistance effect in a Pt/Hf0.5Zr0.5O2/Pt structure,” Appl. Phys. Lett., 110, 9, 093106, 2017.
[31] L. Chen, T.-Y. Wang, Y.-W. Dai, M.-Y. Cha, H. Zhu, Q.-Q. Sun, S.-J. Ding, P. Zhou, L. Chua, D. W. Zhang, “Ultra-low power Hf0.5Zr0.5O2 based ferroelectric tunnel junction synapses for hardware neural network applications,” Nanoscale, 10,15826–15833,2018.
[32] Y. Goh, S. Jeon, “The effect of the bottom electrode on ferroelectric tunnel junctions based on CMOS-compatible HfO2,” Nanotechnology, vol. 29, no. 33, Jun. 2018.
[33] Y.C. Lin, F. McGuire “Realizing ferroelectric Hf0.5Zr0.5O2 with elemental capping layers,” J. Vac. Sci. Technol. B Microelectron. Process. Phenom., vol. 36, 011204, 2018.
[34] B. Max, M. Hoffmann, S. Slesazeck, T. Mikolajick, “Ferroelectric Tunnel Junctions based on Ferroelectric-Dielectric Hf0.5Zr0.5O2/Al2O3 Capacitor Stacks”, in ESSDERC,2018.
[35] R. Cao, Y. Wang, S. Zhao, Y. Yang, X. Zhao, W. Wang, X. Zhang, H. Lv, Q. Liu, M. Liu, “Effects of capping electrode on ferroelectric properties of Hf0.5Zr0.5O2 thin films,” IEEE Electron Device Lett., vol. 39, no. 8, pp. 1207-1210, Jun. 2018.
[36] L. Esaki, R. B. Laibowitz, and P. J. Stiles, “IBM Technical Disclosure Bulletin” 13, 2161, 1971.
[37] M. Kobayashi, Y. Taguwa, F. Mo, T. Saraya, T. Hiramoto, “Ferroelectric HfO2 tunnel junction memory with high TER and multi-level operation featuring metal replacement process,” IEEE J. Electron Dev. Soc., vol. 7, pp. 134–139, 2019.
[38] R. Anderson: “Germanium-Gallium Arsenide Heterojunctions [Letter to the Editor],” IBM J. Res. Dev., 4, 283,1960.
[39] M. Pešić, F.-P.-G. Fengler, L. Larche, A. Padovani, T. Schenk, E. D. Grimley, X. Sang, J. M. LeBeau, S. Slesazeck, U. Schroeder, T. Mikolajick, “Physical Mechanisms behind the Field‐Cycling Behavior of HfO2‐Based Ferroelectric Capacitors,” Adv. Funct. Mater., 26.25, 4601-4612, 2016.
[40] M.H. Park, Y.-H. Lee, H.-J. Kim, Y.- J. Kim, T. Moon, K.-D. Kim, S.-D. Hyun, T. Mikolajick, U. Schroeder, C.-S. Hwang, “Understanding the formation of the metastable ferroelectric phase in hafnia–zirconia solid solution thin films,” Nanoscale, vol. 10, 716-725, 2018.
[41] “Practical Electron Microscopy and Database - Ferroelectric Dielectric Hysteresis & Hysteresis Loop” online book, [online] Available: http://www.globalsino.com/EM/page1804.html
[42] Scott, J. F. “Ferroelectrics go bananas.” Journal of Physics: Condensed Matter, 20.2, 021001, 2007.
[43] B. Dickens, E. Balizer, A. S. DeReggi, S. C. Roth, “Hysteresis measurements of remanent polarization and coercive field in polymers,” J. Appl. Phys., vol. 72, pp. 4258–4264, 1992.
[44] S. Bernacki, E. Balizer, A. S. DeReggi, and S. C. Roth, “Standardized ferroelectric capacitor test methodology for nonvolatile semiconductor memory applications,” Integrated Ferroelectrics, 3.2, 97-112, 1993.
[45] B.T. Lin, Y.-W. Lu, J. Shieh, M.-J. Chen, “Induction of ferroelectricity in nanoscale ZrO2 thin films on Pt electrode without post-annealing,” J. European Ceramic Soc., 37.3, 1135-1139, 2017
[46] T. Kim, G. Baek, S. Yang, J.-Y. Yang, K.-S. Yoon, S.-G. Kim, J.-Y. Lee, H.-S. Im, J.-P. Hong, “Exploring oxygen-affinity-controlled TaN electrodes for thermally advanced TaOx bipolar resistive switching,” Scientific reports, 8.1: 8532, 2018
[47] A. Chanthbouala, V. Garcia, R. O. Cherifi, K.Bouzehouane, S. Fusil, X. Moya, S. Xavier, H. Yamada, C. Deranlot, N. D. Mathur, M. Bibes, A. Barthélémy, J. Grollier, “A ferroelectric memristor,” Nature Mater., vol. 11, pp. 860–864, 2012.
[48] R. Berdan, T. Marukame, S. Kabuyanagi, K. Ota, M. Saitoh, S. Fujii, J. Deguchi, Y. Nishi, “In-memory reinforcement learning with moderately stochastic conductance switching of ferroelectric tunnel junctions,” in Symp. VLSI Tech. Dig., 2019, pp. T22–23.
[49] A. Chanthbouala, A. Crassous, V.Garcia, K. Bouzehouane, S. Fusil, X. Moya, J. Allibe, B. Dlubak, J. Grollier, S. Xavier, C. Deranlot, A. Moshar, R. Proksch, N. D. Mathur, M. Bibes, A. Barthélémy, “Solid-state memories based on ferroelectric tunnel junctions,” Nature Nanotech., vol. 7, pp. 101–104, 2012.
[50] D. J. Kim, H. Lu, S. Ryu, C.-W. Bark, C.-B. Eom, E. Y. Tsymbal, A. Gruverman, “Ferroelectric tunnel memristor,” Nano Lett., vol. 12, pp. 5697–5702, 2012.
[51] H. Yamada, A. T. Fukuchi, M. Kobayashi, Y. Toyosaki, H. Kumingashira, A. Sawa, “Strong surface-termination effect on electroresistance in ferroelectric tunnel junctions,” Adv. Funct. Mater., vol. 25, pp. 2708– 2714, 2015.
[52] M. Kobayashi, Y. Tagawa, F. Mo, T. Saraya, T. Hiramoto, “Ferroelectric HfO2 tunnel junction memory with high TER and multi-level operation featuring metal replacement process,” IEEE J. Electron Dev. Soc., vol. 7, pp. 134–139, 2019.
[53] Z. Fan, J. Xiao, J. Wang, L. Zhang, J. Deng, Z. Liu, Z. Dong, J. Wang, and J. Chen, “Ferroelectricity and ferroelectric resistive switching in sputtered Hf0.5Zr0.5O2 thin films,” Appl. Phys. Lett., vol. 108, 232905, 2016.
[54] H.-H. Huang, T.-Y. Wu, Y.-H. Chu, M.-H. Wu, C.-H. Hsu, H.-Y. Lee, S.-S. Sheu, W.-C. Lo, T.-H. Hou, “A comprehensive modeling framework for ferroelectric tunnel junctions,” in IEDM Tech. Dig., 2019
[55] C.-C.Chang, J.-C.Liu, Y.-L.Shen, T.Chou, P.-C.Chen, I-T.Wang, C.-C.Su, M.-H.Wu, B.Hudec, C.-C.Chang, C.-M.Tsai, T.-S. Chang, H.-S. Philip Wong, T.-H.Hou, “Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network,” in IEDM Tech. Dig., 2017, pp. 278–281.
[56] C.-X. Xue, W.-H. Chen, J.-S. Liu, J.-F. Li, W.-Y. Lin, W.-E. Lin, J.-H. Wang, W.-C. Wei, T.-W. Chang, T.-Ch. Chang, T.-Y. Huang, H.-Y. Kao, S.-Y. Wei, Y.-C. Chiu, C.-Y. Lee, C.-C. Lo, Y.-C. King, C.-J. Lin, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, M.-F. Chang., “A 1Mb multibit ReRAM computing-in-memory macro with 14.6ns parallel MAC computing time for CNN based AI edge processors,” in Proc. ISSCC Tech. Dig., 2019, pp. 388–389.
[57] L. Goux, A. Fantini, R. Degraeve, N. Raghavan, R. Nigon, S. Strangio, G. Kar, D.-J. Wouters, Y.-Y. Chen, M. Komura, F. De Stefano, V.-V. Afanas’ev, M. Jurczak, “Understanding of the intrinsic characteristics and memory trade-offs of sub-μA filamentary RRAM operation,” in Sym. on VLSI Technology, 2013, pp. 162–163.
[58] C. Alessandri, P. Pandey, A. Abusleme, A. Seabaugh, “Switching Dynamics of Ferroelectric Zr-Doped HfO2,” IEEE Electron Device Letters, vol. 39, no. 11, pp. 1780-1783, Nov. 2018.
[59] A. Krizhevsky, I. Sutskever, G. E. Hinton, “Imagenet classification with deep convolutional neural networks,” Proc. 25th Int. Conf. Neural Inf. Process. Syst., pp. 1106-1114, 2012.
[60] T Gokmen, O. M. Onen, W. Haensch., “Training deep convolutional neural networks with resistive cross-point devices,” in Neuroscience 11, 538, 2017.
[61] X.C. Peng, R. Liu, S. Yu, “Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture,” in ISCAS, 2019.
[62] C.-C. Chang, M.-H. Huang, J.-W. Lin, C.-H. Li, V. Parmar, J.-H. Wei, S.-S. Sheu, M. Suri, T.-S. Chang, T.-H. Hou, “NV-BNN: An accurate deep convolutional neural network based on binary STT-MRAM for adaptive AI edge,” in DAC Tech. Dig., 2019.
[63] H. Kim, Y. Kim, J.-J. Kim, “In-memory batch-normalization for resistive memory based binary neural network hardware,” in ASPDAC Tech. Dig., 2019, pp. 645–650.