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研究生:陳雋庭
研究生(外文):Chen, Chun-Ting
論文名稱:以綠光奈秒雷射結晶之低溫多晶矽穿隧式薄膜電晶體之研究
論文名稱(外文):Study on the Characteristics of Low-Temperature Polycrystalline-Silicon Tunnel Thin-Film Transistors via Green Nanoseconds-Laser Crystallization
指導教授:鄭晃忠鄭晃忠引用關係
指導教授(外文):Cheng, Huang-Chung
口試委員:崔秉鉞趙天生汪芳興
口試委員(外文):Tsui, Bing-YueChao, Tien-ShengWang, Fang-Hsing
口試日期:2019-11-05
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:108
語文別:英文
論文頁數:89
中文關鍵詞:薄膜電晶體多晶矽穿隧式電晶體
外文關鍵詞:thin-film transistorspoly-Situnnel FET
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With device scaling, the interconnect delay and power consumption become more and more important, 3D ICs is one of the potential technologies to overcome the issue. Among of 3D packing technologies, the monolithic stacking technology is considered as the promising technique to achieve high-performance 3D stacking technology due to its better alignment performance and easier via process. LTPS TFTs have great potential for upcoming applications to monolithic 3D ICs. However, the leakage current of conventional thin-film transistors (C-TFTs) would be larger due to existence of defect, and the subthreshold swing would be degraded as well, therefore, the power consumption is higher. In addition, C-TFTs would suffer from short channel effect (SCE) with device scaling.
Owing to high potential barrier at off state of TFETs, the leakage current could be suppressed. Moreover, the subthreshold swing of TFETs doesn’t suffer from limitation of 60mV/decade. Thus, TFETs are more energy-efficient. Moreover, TFETs are more immune to short channel effect (SCE), therefore, TFETs also have advantage in device scaling. Thus, we based on the study about C-TFTs in the past to fabricate the tunnel thin-film transistors (T-TFTs), which were expected to have higher potential for monolithic 3D ICs.
In the first part, we proposed the tunnel thin-film transistors via SPC (SPC T-TFTs). The SPC T-TFTs attained the lower off current, higher on/off current ratio. However, the higher subthreshold swing didn’t meet our expectation, and we predicted that the subthreshold swing of SPC T-TFTs could be improved by thinner channel thickness and better crystallinity. SPC T-TFTs had better immunity to channel length scaling, which indicated SPC T-TFTs had advantage in scaling down. Various temperature measurement showed that trap-related current induced higher off current and severe degradation of subthreshold swing. Finally, the impact of channel length in output characteristics was discussed.
In the second part, we proposed the tunnel thin-film transistors via green nanoseconds-laser crystallization (GLC T-TFTs). The GLC T-TFTs attained the lower off current, higher on current, higher on/off current ratio, and lower subthreshold swing, which indicated GLC T-TFTs was more beneficial to utilized in 3D ICs. GLC T-TFTs also showed better immunity to channel length. Due to better crystallinity, the grain boundary trap density (NGB) and interface trap density (Nit) of GLC T-TFTs were smaller. Thus, GLC T-TFTs had better gate controllability. In various temperature measurement, it was indicated that trap-related current induced lower off current and moderate degradation of subthreshold swing. Because the grain boundary distribution of GLC thin films had worse uniformity. Therefore, the uniformity of electrical characteristics for GLC T-TFTs was worse. In addition, the larger surface roughness of GLC thin films also contributed to the variation of electrical characteristics, and even reduced the BTBT current. Finally, the impact of channel length on output characteristics was discussed for GLC T-TFTs as well.
Chinese Abstract i
English Abstract iii
Acknowledgements vi
Contents viii
Table Lists xii
Figure Captions xiii

Chapter 1 Introduction 1
1.1 Overview of the Monolithic Three-Dimensional Integrated Circuits Technology 1
1.2 Crystallization Methods Applied to Si Films 3
1.2.1 Solid-Phase-Crystallization-Based Methods 3
1.2.2 Laser Crystallization Methods 6
1.3 Tunnel Field-Effect Transistors 8
1.4 Various Temperature Measurement 11
1.5 Motivation and Thesis Organization 11

Chapter 2 Experiments 13
2.1 Device Fabrication 13
2.2 Polycrystalline-Silicon Tunnel Thin-Film Transistors via Solid Phase Crystallization Methods 13
2.2.1 Process Flow of Polycrystalline-Silicon Thin Films via Solid Phase Crystallization Methods 13
2.2.2 Process Flow of Polycrystalline-Silicon Thin-Film Transistors via Solid Phase Crystallization Methods 14
2.3 Polycrystalline-Silicon Tunnel Thin-Film Transistors via Green Nanoseconds-Laser Crystallization Methods 14
2.3.1 The Setup of Green Nanoseconds-Laser Annealing System 15
2.3.2 Process Flow of Polycrystalline-Silicon Thin Films via Green Nanoseconds-Laser Crystallization 15
2.3.3 Process Flow of Polycrystalline-Silicon Thin Films Transistors via Green Nanoseconds-Laser Crystallization 16
2.4 Material Analysis 16
2.4.1 Scanning Electron Microscope (SEM) 17
2.4.2 Raman Spectrum Analysis (Raman) 17
2.4.3 Atomic Force Microscope (AFM) 17
2.5 Electrical Measurement 17
2.5.1 Measurement Tool Setup 18
2.5.2 Parameter Definition 18
2.5.2.1 Threshold Voltage 18
2.5.2.2 Subthreshold Swing 18

Chapter 3 Results and Discusstion 19
3.1 Electrical Characteristics of Tunnel Thin Film Transistors via Solid Phase Crystallization 19
3.1.1 Electrical Properties 19
3.1.1.1 Transfer Characteristics 19
3.1.1.2 Impact of Channel Length on Transfer Characteristics 20
3.1.1.3 Extraction of Activation Energy 21
3.1.1.4 Output Characteristics 22
3.1.1.5 Impact of Channel Length on Output Characteristics 23
3.2 Electrical Characteristics of Tunnel Thin-Film Transistors via Green Nanoseconds-Laser Crystallization 25
3.2.1 Material Analysis 25
3.2.1.1 Scanning Electron Microscope (SEM) 25
3.2.1.2 Raman Spectron Analysis 26
3.2.1.3 Atomic Force Microscope (AFM) 27
3.2.2 Electrical Properties 27
3.2.2.1 Transfer Characteristics 27
3.2.2.2 Impact of Trap Density on Transfer Characteristics 28
3.2.2.3 Extraction of Activation Energy 29
3.2.2.4 Uniformity of Transfer Characteristics 29
3.2.2.5 Impact of Surface Roughness on Transfer Characteristics 30
3.2.2.6 Impact of Channel Length on Output Characteristics 31

Chapter 4 Summary and Future Prospects 33
4.1 Summary and Conclusions 33
4.2 Future Prospects 35

Tables 36
Chapter 1 36
Chapter 2 37
Chapter 3 38
Figures 43
Chapter 1 43
Chapter 2 52
Chapter 3 57
References 83
Vita 89
[1] J. Knechtel, "Interconnect Planning for Physical Design of 3D Integrated Circuits," Saechsische Landesbibliothek-Staats-und Universitaetsbibliothek Dresden, 2014.
[2] L. Xiu, "Time Moore: Exploiting Moore's Law From The Perspective of Time," IEEE Solid-State Circuits Magazine, vol. 11, no. 1, pp. 39-55, 2019.
[3] E. P. DeBenedictis, M. Badaroglu, A. Chen, T. M. Conte, and P. Gargini, "Sustaining Moore's law with 3D chips," Computer, vol. 50, no. 8, pp. 69-73, 2017.
[4] K. C. Saraswat, "3-D ICs: Motivation, performance analysis, technology and applications," in 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2010, pp. 1-6: IEEE.
[5] P. Batude et al., "Advances, challenges and opportunities in 3D CMOS sequential integration," in 2011 International Electron Devices Meeting, 2011, pp. 7.3. 1-7.3. 4: IEEE.
[6] A. Mimura et al., "High performance low-temperature poly-Si n-channel TFTs for LCD," IEEE Transactions on Electron Devices, vol. 36, no. 2, pp. 351-359, 1989.
[7] A. Voutsas, "A new era of crystallization: advances in polysilicon crystallization and crystal engineering," Applied Surface Science, vol. 208, pp. 250-262, 2003.
[8] I.-C. Lee, T.-C. Tsai, C.-C. Tsai, P.-Y. Yang, C.-L. Wang, and H.-C. Cheng, "High-performance vertically stacked bottom-gate and top-gate polycrystalline silicon thin-film transistors for three-dimensional integrated circuits," Solid-State Electronics, vol. 77, pp. 26-30, 2012.
[9] S. Takenaka, M. Kunii, H. Oka, and H. Kurihara, "High mobility poly-Si thin film transistors using solid phase crystallized a-Si films deposited by plasma-enhanced chemical vapor deposition," Japanese journal of applied physics, vol. 29, no. 12A, p. L2380, 1990.
[10] Z. Jin, G. A. Bhat, M. Yeung, H. S. Kwok, and M. Wong, "Nickel induced crystallization of amorphous silicon thin films," Journal of Applied Physics, vol. 84, no. 1, pp. 194-200, 1998.
[11] C.-H. Chou et al., "Effects of crystallization mechanism on the electrical characteristics of green continuous-wave-laser-crystallized polycrystalline silicon thin film transistors," Applied Physics Letters, vol. 103, no. 5, p. 053515, 2013.
[12] A. Mimura et al., "High-performance low-temperature poly-Si TFTs for LCD," in 1987 International Electron Devices Meeting, 1987, pp. 436-439: IEEE.
[13] R. Iverson and R. Reif, "Recrystallization of amorphized polycrystalline silicon films on SiO2: Temperature dependence of the crystallization parameters," Journal of applied physics, vol. 62, no. 5, pp. 1675-1681, 1987.
[14] A. Nakamura et al., "Analysis of solid phase crystallization in amorphized polycrystalline Si films on quartz substrates," Journal of Applied Physics, vol. 66, no. 9, pp. 4248-4251, 1989.
[15] R. Nemanich, C. Tsai, M. Thompson, and T. Sigmon, "Interference enhanced Raman scattering study of the interfacial reaction of Pd on a‐Si: H," Journal of Vacuum Science and Technology, vol. 19, no. 3, pp. 685-688, 1981.
[16] L. Hultman, A. Robertsson, H. Hentzell, I. Engström, and P. Psaras, "Crystallization of amorphous silicon during thin‐film gold reaction," Journal of applied physics, vol. 62, no. 9, pp. 3647-3655, 1987.
[17] Y. Kawazu, H. Kudo, S. Onari, and T. Arai, "Low-temperature crystallization of hydrogenated amorphous silicon induced by nickel silicide formation," Japanese journal of applied physics, vol. 29, no. 12R, p. 2698, 1990.
[18] G. Radnoczi, A. Robertsson, H. Hentzell, S. Gong, and M. A. Hasan, "Al induced crystallization of a‐Si," Journal of Applied physics, vol. 69, no. 9, pp. 6394-6399, 1991.
[19] C. Hayzelden and J. Batstone, "Silicide formation and silicide‐mediated crystallization of nickel‐implanted amorphous silicon thin films," Journal of Applied Physics, vol. 73, no. 12, pp. 8279-8289, 1993.
[20] S.-W. Lee and S.-K. Joo, "Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization," IEEE Electron Device Letters, vol. 17, no. 4, pp. 160-162, 1996.
[21] S. Jagar et al., "Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization," in International Electron Devices Meeting 1999. Technical Digest (Cat. No. 99CH36318), 1999, pp. 293-296: IEEE.
[22] S. Y. Yoon, J. Y. Oh, C. O. Kim, and J. Jang, "Low temperature solid phase crystallization of amorphous silicon at 380 C," Journal of applied physics, vol. 84, no. 11, pp. 6463-6465, 1998.
[23] M. Kurosawa, N. Kawabata, T. Sadoh, and M. Miyao, "Orientation-controlled Si thin films on insulating substrates by Al-induced crystallization combined with interfacial-oxide layer modulation," Applied Physics Letters, vol. 95, no. 13, p. 132103, 2009.
[24] T.-H. Ihn, T.-K. Kim, B.-I. Lee, and S. K. Joo, "A study on the leakage current of poly-Si TFTs fabricated by metal induced lateral crystallization," Microelectronics Reliability, vol. 39, no. 1, pp. 53-58, 1999.
[25] T. Sameshima, M. Hara, and S. Usui, "Measuring the Temperature of a Quartz Substrate during and after the Pulsed Laser-Induced Crystallization of a-Si: H," Japanese journal of applied physics, vol. 28, no. 12A, p. L2131, 1989.
[26] H. Kuriyama et al., "Enlargement of poly-Si film grain size by excimer laser annealing and its application to high-performance poly-Si thin film transistor," Japanese journal of applied physics, vol. 30, no. 12S, p. 3700, 1991.
[27] T. Sameshima, S. Usui, and M. Sekiya, "XeCl excimer laser annealing used in the fabrication of poly-Si TFT's," IEEE Electron Device Letters, vol. 7, no. 5, pp. 276-278, 1986.
[28] R. S. Sposili and J. S. Im, "Sequential lateral solidification of thin silicon films on SiO2," Applied Physics Letters, vol. 69, no. 19, pp. 2864-2866, 1996.
[29] M. O. Thompson et al., "Melting temperature and explosive crystallization of amorphous silicon during pulsed laser irradiation," Physical review letters, vol. 52, no. 26, p. 2360, 1984.
[30] A. Hara et al., "High performance poly-Si TFTs on a glass by a stable scanning CW laser lateral crystallization," in International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), 2001, pp. 34.2. 1-34.2. 4: IEEE.
[31] J. Michaud, R. Rogel, T. Mohammed-Brahim, and M. Sarret, "CW argon laser crystallization of silicon films: structural properties," Journal of non-crystalline solids, vol. 352, no. 9-20, pp. 998-1002, 2006.
[32] J. Yun, S. Varlamov, J. Huang, K. Kim, and M. Green, "Effect of deposition temperature on electron-beam evaporated polycrystalline silicon thin-film and crystallized by diode laser," Applied Physics Letters, vol. 104, no. 24, p. 242102, 2014.
[33] D. Basting, K. D. Pippert, and U. Stamm, "History and future prospects of excimer lasers," in Second International Symposium on Laser Precision Microfabrication, 2002, vol. 4426, pp. 25-34: International Society for Optics and Photonics.
[34] P. Dyer and H. Snelling, "Gas lasers for medical applications," in Lasers for Medical Applications: Elsevier, 2013, pp. 177-202.
[35] J. S. Im, H. Kim, and M. O. Thompson, "Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon films," Applied Physics Letters, vol. 63, no. 14, pp. 1969-1971, 1993.
[36] F. Voogt, R. Ishihara, and F. Tichelaar, "Melting and crystallization behavior of low-pressure chemical-vapor-deposition amorphous Si films during excimer-laser annealing," Journal of applied physics, vol. 95, no. 5, pp. 2873-2879, 2004.
[37] J. S. Im and H. Kim, "On the super lateral growth phenomenon observed in excimer laser‐induced crystallization of thin Si films," Applied Physics Letters, vol. 64, no. 17, pp. 2303-2305, 1994.
[38] S. Fujii, S.-I. Kuroki, X. Zhu, M. Numata, K. Kotani, and T. Ito, "Analysis of continuous-wave laser lateral crystallized polycrystalline silicon thin films with large tensile strain," Japanese Journal of Applied Physics, vol. 47, no. 4S, p. 3046, 2008.
[39] C.-C. Yang et al., "Enabling low power BEOL compatible monolithic 3D+ nanoelectronics for IoTs using local and selective far-infrared ray laser anneal technology," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 8.7. 1-8.7. 4: IEEE.
[40] C.-C. Yang et al., "Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate," in 2013 IEEE International Electron Devices Meeting, 2013, pp. 29.6. 1-29.6. 4: IEEE.
[41] C.-C. Yang et al., "High gamma value 3D-stackable HK/MG-stacked tri-gate nanowire poly-Si FETs with embedded source/drain and back gate using low thermal budget green nanosecond laser crystallization technology," IEEE Electron Device Letters, vol. 37, no. 5, pp. 533-536, 2016.
[42] A. Chaudhry and M. J. Kumar, "Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review," IEEE Transactions on Device and Materials Reliability, vol. 4, no. 1, pp. 99-109, 2004.
[43] A. M. Ionescu and H. Riel, "Tunnel field-effect transistors as energy-efficient electronic switches," nature, vol. 479, no. 7373, p. 329, 2011.
[44] A. C. Seabaugh and Q. Zhang, "Low-voltage tunnel transistors for beyond CMOS logic," Proceedings of the IEEE, vol. 98, no. 12, pp. 2095-2110, 2010.
[45] S. M. Turkane and A. Kureshi, "Review of tunnel field effect transistor (TFET)," International Journal of Applied Engineering Research, vol. 11, no. 7, pp. 4922-4929, 2016.
[46] E. Kane, "Zener tunneling in semiconductors," Journal of Physics and Chemistry of Solids, vol. 12, no. 2, pp. 181-188, 1960.
[47] J.-T. Lin, K.-D. Huang, and S.-F. Hu, "Non-classical polycrystalline silicon thin-film transistor with embedded block-oxide for suppressing the short channel effect," Semiconductor Science and Technology, vol. 23, no. 7, p. 075007, 2008.
[48] A. G. Lewis, T. Y. Huang, I.-W. Wu, R. H. Bruce, and A. Chiang, "Physical mechanisms for short channel effects in polysilicon thin films transistors," in International Technical Digest on Electron Devices Meeting, 1989, pp. 349-352: IEEE.
[49] A. G. Lewis, I.-W. Wu, T. Y. Huang, M. Koyanagi, A. Chiang, and R. H. Bruce, "Small geometry effects in n-and p-channel polysilicon thin film transistors," in Technical Digest., International Electron Devices Meeting, 1988, pp. 260-263: IEEE.
[50] M.-H. Juang, Y.-S. Peng, D.-C. Shye, J.-L. Wang, C.-C. Hwang, and S.-L. Jang, "Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer," Microelectronic Engineering, vol. 88, no. 1, pp. 32-35, 2011.
[51] D. Leonelli et al., "Silicide engineering to boost Si tunnel transistor drive current," Japanese Journal of Applied Physics, vol. 50, no. 4S, p. 04DC05, 2011.
[52] Y.-H. Chen, L.-C. Yen, T.-S. Chang, T.-Y. Chiang, P.-Y. Kuo, and T.-S. Chao, "Low-temperature polycrystalline-silicon tunneling thin-film transistors with MILC," IEEE Electron Device Letters, vol. 34, no. 8, pp. 1017-1019, 2013.
[53] H.-C. Cheng, F.-S. Wang, and C.-Y. Huang, "Effects of NH/sub 3/plasma passivation on N-channel polycrystalline silicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 44, no. 1, pp. 64-68, 1997.
[54] W. C.-Y. Ma, H.-S. Hsu, C.-C. Fang, C.-Y. Jao, and T.-H. Liao, "Impacts of channel film thickness on poly-Si tunnel thin-film transistors," Thin Solid Films, vol. 660, pp. 926-930, 2018.
[55] W. C.-Y. Ma, T.-Y. Chiang, C.-R. Yeh, T.-S. Chao, and T.-F. Lei, "Channel film thickness effect of low-temperature polycrystalline-silicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 58, no. 4, pp. 1268-1272, 2011.
[56] W. C.-Y. Ma and Y.-H. Chen, "Performance improvement of poly-Si tunnel FETs by trap density reduction," IEEE Transactions on Electron Devices, vol. 63, no. 2, pp. 864-868, 2015.
[57] R. N. Sajjad, W. Chern, J. L. Hoyt, and D. A. Antoniadis, "Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs," IEEE Transactions on Electron Devices, vol. 63, no. 11, pp. 4380-4387, 2016.
[58] S. Richter et al., "Omega-Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs," IEEE Electron Device Letters, vol. 33, no. 11, pp. 1535-1537, 2012.
[59] S. Mookerjea and S. Datta, "Band-gap engineered hot carrier tunnel transistors," in 2009 Device Research Conference, 2009, pp. 121-122: IEEE.
[60] G. Hurkx, D. Klaassen, and M. Knuvers, "A new recombination model for device simulation including tunneling," IEEE Transactions on electron devices, vol. 39, no. 2, pp. 331-338, 1992.
[61] G. Armstrong, S. Brotherton, and J. Ayres, "A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors," Solid-State Electronics, vol. 39, no. 9, pp. 1337-1346, 1996.
[62] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, "Floating body effects in polysilicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 44, no. 12, pp. 2234-2241, 1997.
[63] C. Wang, C. Wu, J. Wang, Q. Huang, and R. Huang, "Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling," Science China Information Sciences, vol. 58, no. 2, pp. 1-8, 2015.
[64] P. Ghosh and B. Bhowmick, "Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance," Journal of Computational Electronics, pp. 1-10, 2019.
[65] B. Bhowmick, S. Baishya, and R. Kar, "Length scaling of Hetero-gate dielectric SOI PNPN TFET," in 2011 Annual IEEE India Conference, 2011, pp. 1-4: IEEE.
[66] M. Hack, A. Lewis, and J. Shaw, "Influence of traps on the characteristics of thin film transistors," Journal of non-crystalline solids, vol. 137, pp. 1229-1232, 1991.
[67] R. Proano, R. Misage, and D. Ast, "Development and electrical properties of undoped polycrystalline silicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 36, no. 9, pp. 1915-1922, 1989.
[68] C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitriou, and N. Economou, "Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures," IEEE Transactions on Electron Devices, vol. 39, no. 3, pp. 598-606, 1992.
[69] Y.-H. Chen et al., "Impact of crystallization method on poly-Si tunnel FETs," IEEE Electron Device Letters, vol. 36, no. 10, pp. 1060-1062, 2015.
[70] F. Conzatti, M. Pala, and D. Esseni, "Surface-roughness-induced variability in nanowire InAs tunnel FETs," IEEE Electron Device Letters, vol. 33, no. 6, pp. 806-808, 2012.
[71] H. Carrillo-Nunez, R. Rhyner, M. Luisier, and A. Schenk, "Effect of surface roughness and phonon scattering on extremely narrow InAs-Si Nanowire TFETs," in 2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, pp. 188-191: IEEE.
[72] C.-C. Tsai et al., "Polycrystalline silicon thin-film transistors with location-controlled crystal grains fabricated by excimer laser crystallization," Applied Physics Letters, vol. 91, no. 20, p. 201903, 2007.
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