臺灣博碩士論文加值系統

本論文主要探討電荷擷取式快閃記憶體(charge trap flash memory)中主要之可靠度效應，其中包含保存狀態(retention)時儲存電荷之橫向遷移(charge lateral migration)，以及其在不同資料儲存模式(data pattern effects)下對臨界電壓(Vt)隨資料儲存時間變化之影響。另外，電荷橫向傳輸之物理機制亦在本論文中有進一步之分析驗證。

第一章首先介紹近年來NAND快閃記憶體的發展演進以及現今三維快閃記憶體(3D NAND flash memory)架構下之不同型態差異。其次，三維垂直通道(vertical channel)電荷擷取式快閃記憶體之可靠度議題將在此章節說明。另外，吾人亦指出氮化矽儲存層電荷橫向遷移及其在不同資料儲存模式下對資料儲存時間之影響皆為3D NAND中重要之議題，而由電子及電洞橫向移動所造成之轉折(turn-around)特性亦將在此詳述。本章節的最後一部分針對此論文之整體架構做概略性的介紹。

第二章主要探討儲存電荷在保存狀態時橫向傳輸之物理機制。吾人比較熱助穿隧(thermally assisted tunneling)、Frenkel-Poole躍遷(emission)、直接穿隧(direct trap-to-band tunneling)與hopping四種機制之躍遷速率，根據模型計算之結果，熱助穿隧被認為是主導電荷橫向移動最有效率之躍遷機制，此結論於大多數的電場範圍之下皆為適用。

第三章中，吾人探討單一SONOS快閃記憶元件中電場引致內部儲存電子橫向傳輸之行為。元件在保存狀態之電子遷移現象可反映在臨界電壓變化和閘極引致汲極漏電電流(GIDL)的變化，藉由改變閘極電壓及源極電壓，吾人可分別調整保存狀態時的垂直電場和水平電場，研究結果顯示閘極引致汲極漏電電流變化的量測可偵測儲存電子的橫向傳輸情形。另外，吾人也發現電荷的橫向傳輸具有明顯的電場效應，根據量測所得之電場與溫度效應，吾人所提出之「熱助穿隧」模型可用來詮釋並預測電子橫向傳輸之程度。

第四章主要藉由隨機電報雜訊(RTS)之方法來探討電荷擷取式快閃記憶體中內部電洞之橫向傳輸行為。該實驗的理論基礎如下：藉由量測隨機電報雜訊之電流訊號，其對應的氧化層缺陷(trap)之電位改變則可被偵測用以分析氮化矽儲存層內部電洞的橫向運動程度。吾人改變元件保存狀態時的外加電壓與溫度，進一步分析電洞橫向遷移與電場及溫度之關係，根據實驗所萃取之活化能(thermal energy)與理論模型的分析比較，吾人推斷「熱助穿隧」模型為電洞在氮化矽中橫向傳輸之主要機制。

在第五章，吾人主要探討電荷擷取式快閃記憶體中氮化矽內部電荷橫向傳輸以及其在不同資料儲存模式下對臨界電壓隨資料儲存時間變化之影響，吾人採用單一SONOS元件並利用通道熱電子效應(channel hot electron program)和能帶至能帶熱電洞穿隧效應(band-to-band tunneling hot hole erase)兩種機制分別於儲存層靠近通道兩端之處注入電子和電洞，並調整電子/電洞的注入量來模仿3D NAND中的不同資料儲存模式，同時利用隨機電報雜訊方式來辨別電子或電洞之橫向移動情況。藉由改變元件保存狀態時的閘極電壓及源/汲極電壓，並記錄隨機電報雜訊及臨界電壓變化之結果，吾人得以區分電子垂直方向流失、電子橫向遷移與電洞橫向遷移於多種資料儲存模式下對臨界電壓之影響程度。此外，由於電子與電洞之間存在交互作用之緣故，吾人發現隨著寫入程度(program level)的上升，其臨界電壓之變化量呈現一轉折之特性，透過吾人的研究分析將得到以下之結論：於較低的寫入程度情況下，臨界電壓變化由相鄰儲存位元之電洞橫向遷移所造成；反之，於較高的寫入程度情況下，電洞橫向遷移之影響降低，而臨界電壓變化則由該位元之電子垂直方向流失及電子橫向遷移所致。

最後於第六章，吾人將對本論文做個總結。

This dissertation will focus on major reliability issues in charge trap flash memory. The reliability issues, such as trapped charge lateral migration in silicon nitride during a retention bake, and data pattern effects on Vt retention loss are characterized. The physical mechanism responsible for trapped charge lateral transport is also investigated.

In Chapter 1, first, the evolution of the NAND flash memory technology in recent years and the different types of 3D NAND architectures are addressed. Second, several new challenges and reliability issues in 3D vertical channel charge trap flash memory are introduced. Also, the impact of the trapped charge lateral migration in silicon nitride and the data pattern effect in 3D NAND flash are pointed out. Finally, a peculiar turn-around feature originated from electron and hole movement is described. The organization of this dissertation will be given in this chapter.

Mechanisms of charge lateral transport in retention are investigated in Chapter 2. We compare the emission rates of thermally assisted tunneling (ThAT), Frenkel-Poole (FP) emission, direct trap-to-band tunneling (DT), and hopping. According to the modeled results, we believe that ThAT is the most efficient charge emission process for charge lateral movement in a wide range of electric fields.

In Chapter 3, we explore electric field-induced trapped electron lateral migration in a SONOS flash cell. The threshold voltage shift and gate-induced drain leakage (GIDL) current are measured to monitor nitride electron movement in retention. We apply different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that i) GIDL current can be used to monitor trapped electron lateral migration and ii) nitride electron lateral migration exhibits strong dependence on the lateral electric field. Based on the measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration.

In Chapter 4, we use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal (RTS) as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport.

In Chapter 5, we investigate electron and hole lateral migration and data pattern effect on Vt retention loss in a multi-level charge trap flash memory. We use hot electron program and band-to-band tunneling hot hole erase to inject various amounts of electrons and holes at the two ends of a SONOS cell. A random telegraph signal (RTS) method is used to distinguish electron and hole lateral movements in silicon nitride. In Vt retention measurement, we apply a voltage to the gate or the source/drain to enhance or retard trapped charge vertical loss and lateral migration. From the evolution characteristics of RTS and Vt traces in retention, we are able to identify the separate roles of electron vertical loss, electron lateral migration, and hole lateral migration in different data patterns. Due to the interaction of stored electrons and holes, we find that Vt retention loss in a program state exhibits a turn-around characteristic as program Vt level increases. Vt loss at low program levels is attributed to hole lateral migration from a neighboring bit. At higher program levels, the influence of hole lateral migration is reduced and Vt loss is dominated by electron vertical loss and lateral migration.

Finally, conclusions are made in Chapter 6.

Chinese Abstract i
English Abstract iv
Acknowledgement viii
Contents x
Table Caption xiii
Figure Captions xiv
List of Symbols xxii

Chapter 1 Introduction 1
1.1 Background 1
1.2 Description of the Problems 2
1.3 Organization of the Dissertation 5

Chapter 2 Physical Mechanisms of Trapped Charge Lateral Transport in Silicon Nitride 15
2.1 Preface 15
2.2 Trapped Charge Emission Mechanisms 16
2.3 Carrier Lateral Transport Mechanisms 19
2.4 Temperature and Electric Field Dependences 20
2.5 Summary 21

Chapter 3 Electric Field Induced Nitride Trapped Electron Lateral Migration in a SONOS Flash Memory 26
3.1 Preface 26
3.2 Device Characterization of a SONOS Cell 26
3.3 Characterization of Electron Lateral Migration by Using a GIDL Method 27
3.3.1 Evidence of Electron Lateral Migration 27
3.3.2 Electric Field Effects 28
3.3.3 Temperature Effects 29
3.4 Validation of Thermally Assisted Tunneling Model 30
3.5 Summary 31

Chapter 4 Characterization of Nitride Hole Lateral Transport in a Charge Trap Flash Memory by Using a Random Telegraph Signal Method 42
4.1 Preface 42
4.2 Device Characterization of a SONOS Cell 43
4.3 Random Telegraph Signal Method 43
4.3.1 Extraction of an RTS Trap Position in the Channel 43
4.3.2 Concept of an RTS Characterization Method 45
4.4 Electric Field and Temperature Effects on Trapped Hole Lateral Migration 46
4.5 Validation of Thermally Assisted Tunneling Model 46
4.6 Summary 47

Chapter 5 Investigation of Data Pattern Effects on Vt Retention Loss in a Multi-Level Charge Trap Flash Memory 58
5.1 Preface 58
5.2 Cell Characteristics and RTS Method 60
5.3 Electron Vertical Loss in Retention 61
5.4 Electron and Hole Lateral Movement in Vt Loss 62
5.5 Causes of Vt Loss in Different Program Levels 65
5.5.1 The Roles of Electron and Hole Lateral Migration in Different Program Levels 65
5.5.2 The Causes of a Turn-Around Characteristic 66
5.6 Summary 68

Chapter 6 Conclusions 90

References 92
Vita 111
Publication List 112

References
Chapter 1

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Chapter 2

[2.1] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit cost scalable technology with punch and plug process for ultra high density flash memory,” in VLSI Symp. Tech. Dig., 2007, pp. 14−15.
[2.2] J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D. W. Kim, K. Kim, J.-J. Shim, J. S. Lim, K.-H. Kim, S. Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Son, U-I. Chung, and W.-S. Lee, “Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory,” in VLSI Symp. Tech. Dig., 2009, pp. 192−193.
[2.3] W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, T. Wang, S. Pan, and C.-Y. Lu, “Cause of data retention loss in a nitride-based localized trapping storage flash memory cell,” in Proc. IEEE Int. Rel. Phys. Symp., 2002, pp. 34−38.
[2.4] Y. Roizin and V. Gritsenko, “ONO structures and oxynitrides in modern microelectronics: material science, characterization and application,” in Dielectric Films for Advanced Microelectronics, M. Baklanov, K. Maex, and M. Green, Ed. Chichester, U.K.: Wiley, 2007, pp. 251−295.
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[2.6] S.-H. Gu, C.-W. Hsu, T. Wang, W.-P. Lu, Y.-H. Joseph Ku, and C.-Y. Lu, “Numerical simulation of bottom oxide thickness effect on charge retention in SONOS flash memory cells,” IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 90−97, Jan. 2007.
[2.7] A. Maconi, A. Arreghini, C. Monzio Compagnoni, G. Van den bosch, A. S. Spinelli, J. Van Houdt, and A. L. Lacaita, “Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices,” Solid State Electron., vol. 74, no. 8, pp. 64−70, Aug. 2012.
[2.8] Y.-H. Liu, C.-M. Jiang, W.-C. Chen, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Electric field induced nitride trapped charge lateral migration in a SONOS flash memory,” IEEE Electron Device Lett., vol. 38, no. 1, pp. 48−51, Jan. 2017.
[2.9] G. G. Roberts and J. I. Polanco, “Thermally assisted tunneling in dielectric films,” Phys. Status Solidi (a), vol. 1, pp. 409−420, 1970.
[2.10] S. M. Sze, Physics of Semiconductors Devices. New York: Wiley, 1981.
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[2.13] Y.-H. Liu, C.-M. Jiang, H.-Y. Lin, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method,” Appl. Phys. Lett., vol. 111, no. 3, p. 033501, Jul. 2017.
[2.14] Y. H. Liu, H. Y. Lin, C. M. Jiang, T. Wang, W. J. Tsai, T. C. Lu, K. C. Chen, and C.-Y. Lu, “Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method,” in Proc. IEEE Int. Rel. Phys. Symp., 2018, pp. 6D.1-1–6D.1-5.
[2.15] E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, N. Akil, M. J. van Duuren, and D. S. Golubovć, “Experimental and simulation analysis of program/retention transients in silicon nitride-based NVM cells,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1980−1990, Sep. 2009.
[2.16] Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, “Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 540−542, Nov. 2000.
[2.17] A. V. Shaposhnikov, I. P. Petrov, V. A. Gritsenko, and C. W. Kim, “Electronic band structure and effective masses of electrons and holes in the  and  phases of silicon nitride,” Phys. Solid State, vol. 49, no. 9, pp. 1628−1632, Sep. 2007.
[2.18] A. Suhane, A. Arreghini, R. Degraeve, G. Van den bosch, L. Breuil, M. B. Zahid, M. Jurczak, K. De Meyer, and J. Van Houdt, “Validation of retention modeling as a trap-profiling technique for SiN-based charge-trapping memories,” IEEE Electron Device Lett., vol. 31, no. 1, pp. 77−79, Jan. 2010.
[2.19] Y.-Y. Liao, S.-F. Horng, Y.-W. Chang, T.-C. Lu, K.-C. Chen, T. Wang, and C.-Y. Lu, “profiling of nitride-trap-energy distribution in SONOS flash memory by using a variable-amplitude low-frequency charge-pumping technique,” IEEE Electron Device Lett., vol. 28, no. 9, pp. 828−830, Sep. 2007.
[2.20] H.-T. Lue, S.-Y. Wang, Y.-H. Hsiao, E.-K. Lai, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu, and C. Y. Lu, “Reliability model of bandgap engineered SONOS (BE-SONOS),” in IEDM Tech. Dig., 2006, pp. 495−498.
[2.21] A. Arreghini, N. Akil, F. Driussi, D. Esseni, L. Selmi, and M. J. Van Duuren, “Long term charge retention dynamics of SONOS cells,” Solid State Electron., vol. 52, no. 9, pp. 1460−1466, Sep. 2008.
[2.22] H.-C. Ma, Y.-L. Chou, J.-P. Chiu, Y.-T. Chung, T.-Y. Lin, T. Wang, Y.-P. Chao, K.-C. Chen, and C.-Y. Lu, “A novel random telegraph signal method to study program/erase charge lateral spread and retention loss in a SONOS flash memory,” IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 623−630, Mar. 2011.
[2.23] B. Choi, S. H. Jang, J. Yoon, J. Lee, M. Jeon, Y. Lee, J. Han, J. Lee, D. M. Kim, D. H. Kim, C. Lim, S. Park, and S.-J. Choi, “Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory,” in VLSI Symp. Tech. Dig., 2016, pp. 78−79.
[2.24] İ. Ay, and H. Tolunay, “Steady-state and transient photoconductivity in hydrogenated amorphous silicon nitride films,” Sol. Energy Mater. Sol. Cells, vol. 80, pp. 209−216, 2003.
[2.25] A. Padovani, A. Arreghini, L. Vandelli, L. Larcher, G. Van den bosch, P. Pavan, and J. Van Houdt, “A comprehensive understanding of the erase of TANOS memories through charge separation experiments and simulations,” IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3147−3155, Sep. 2011.

Chapter 3

[3.1] A. Maconi, A. Arreghini, C. Monzio Compagnoni, G. Van den bosch, A. S. Spinelli, J. Van Houdt, and A. L. Lacaita, “Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices,” Solid State Electron., vol. 74, no. 8, pp. 64−70, Aug. 2012.
[3.2] L. Liu, A. Arreghini, G. Van den bosch, L. Pan, and J. Van Houdt, “Assessment methodology of the lateral migration component in data retention of 3D SONOS memories,” Microelectronics reliability, vol. 54, no. 9−10, pp. 1697−1701, Aug. 2014.
[3.3] H.-J. Kang, N. Choi, S.-M. Joe, J.-H. Seo, E. Choi, S.-K. Park, B.-G. Park, and J.-H. Lee, “Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure,” in VLSI Symp. Tech. Dig., 2015, pp. T182−T183.
[3.4] B. Choi, S. H. Jang, J. Yoon, J. Lee, M. Jeon, Y. Lee, J. Han, J. Lee, D. M. Kim, D. H. Kim, C. Lim, S. Park, and S.-J. Choi, “Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory,” in VLSI Symp. Tech. Dig., 2016, pp. 78−79.
[3.5] K. Mizoguchi, S. Kotaki, Y. Deguchi, and K. Takeuchi, “Lateral charge migration suppression of 3D-NAND flash by VTH nearing for near data computing,” in IEDM Tech. Dig., 2017, pp. 465−468.
[3.6] T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” in IEDM Tech. Dig., 1987, pp. 718−721.
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[3.8] T. Wang, T.-E. Chang, L.-P. Chiang, C.-H. Wang, N.-K. Zous, and C. Huang, “Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique,” IEEE Trans. Electron Devices, vol. 45, no. 7, pp. 1511−1517, Jul. 1998.
[3.9] Y.-H. Liu, C.-M. Jiang, W.-C. Chen, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Electric field induced nitride trapped charge lateral migration in a SONOS flash memory,” IEEE Electron Device Lett., vol. 38, no. 1, pp. 48−51, Jan. 2017.
[3.10] H.-C. Ma, Y.-L. Chou, J.-P. Chiu, Y.-T. Chung, T.-Y. Lin, T. Wang, Y.-P. Chao, K.-C. Chen, and C.-Y. Lu, “A novel random telegraph signal method to study program/erase charge lateral spread and retention loss in a SONOS flash memory,” IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 623−630, Mar. 2011.
[3.11] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C.-Y. Lu, and S. H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” in IEDM Tech. Dig., 2001, pp. 719−722.
[3.12] ISE TCAD Manual Release 10.0, Integr. Syst. Eng., Zurich, Switzerland, 2004.
[3.13] Y. Roizin and V. Gritsenko, “ONO structures and oxynitrides in modern microelectronics: material science, characterization and application,” in Dielectric Films for Advanced Microelectronics, M. Baklanov, K. Maex, and M. Green, Ed. Chichester, U.K.: Wiley, 2007, pp. 251−295.
[3.14] S. M. Sze, Physics of Semiconductors Devices. New York: Wiley, 1981.
[3.15] Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, “Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 540−542, Nov. 2000.
[3.16] A. V. Shaposhnikov, I. P. Petrov, V. A. Gritsenko, and C. W. Kim, “Electronic band structure and effective masses of electrons and holes in the  and  phases of silicon nitride,” Phys. Solid State, vol. 49, no. 9, pp. 1628−1632, Sep. 2007.
[3.17] A. Suhane, A. Arreghini, R. Degraeve, G. Van den bosch, L. Breuil, M. B. Zahid, M. Jurczak, K. De Meyer, and J. Van Houdt, “Validation of retention modeling as a trap-profiling technique for SiN-based charge-trapping memories,” IEEE Electron Device Lett., vol. 31, no. 1, pp. 77−79, Jan. 2010.
[3.18] Y.-Y. Liao, S.-F. Horng, Y.-W. Chang, T.-C. Lu, K.-C. Chen, T. Wang, and C.-Y. Lu, “Profiling of nitride-trap-energy distribution in SONOS flash memory by using a variable-amplitude low-frequency charge-pumping technique,” IEEE Electron Device Lett., vol. 28, no. 9, pp. 828−830, Sep. 2007.
[3.19] H.-T. Lue, S.-Y. Wang, Y.-H. Hsiao, E.-K. Lai, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu, and C. Y. Lu, “Reliability model of bandgap engineered SONOS (BE-SONOS),” in IEDM Tech. Dig., 2006, pp. 495−498.
[3.20] E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, N. Akil, M. J. van Duuren, and D. S. Golubovć, “Experimental and simulation analysis of program/retention transients in silicon nitride-based NVM cells,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1980−1990, Sep. 2009.
[3.21] İ. Ay, and H. Tolunay, “Steady-state and transient photoconductivity in hydrogenated amorphous silicon nitride films,” Sol. Energy Mater. Sol. Cells, vol. 80, pp. 209−216, 2003.
[3.22] A. Padovani, A. Arreghini, L. Vandelli, L. Larcher, G. Van den bosch, P. Pavan, and J. Van Houdt, “A comprehensive understanding of the erase of TANOS memories through charge separation experiments and simulations,” IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3147−3155, Sep. 2011.

Chapter 4

[4.1] Y.-H. Liu, C.-M. Jiang, H.-Y. Lin, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method,” Appl. Phys. Lett., vol. 111, no. 3, p. 033501, Jul. 2017.
[4.2] B. Choi, S. H. Jang, J. Yoon, J. Lee, M. Jeon, Y. Lee, J. Han, J. Lee, D. M. Kim, D. H. Kim, C. Lim, S. Park, and S.-J. Choi, “Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory,” in VLSI Symp. Tech. Dig., 2016, pp. 78−79.
[4.3] W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, T. Wang, S. Pan, and C.-Y. Lu, “Cause of data retention loss in a nitride-based localized trapping storage flash memory cell,” in Proc. IEEE Int. Rel. Phys. Symp., 2002, pp. 34−38.
[4.4] H.-C. Ma, Y.-L. Chou, J.-P. Chiu, Y.-T. Chung, T.-Y. Lin, T. Wang, Y.-P. Chao, K.-C. Chen, and C.-Y. Lu, “A novel random telegraph signal method to study program/erase charge lateral spread and retention loss in a SONOS flash memory,” IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 623−630, Mar. 2011.
[4.5] P. Bharath Kumar, P. R. Nair, R. Sharma, S. Kamohara, and S. Mahapatra, “Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 698−705, Apr. 2006.
[4.6] Y.-H. Liu, C.-M. Jiang, H.-Y. Lin, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method,” Appl. Phys. Lett., vol. 111, no. 3, p. 033501, Jul. 2017.
[4.7] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, ”Random telegraph noise of deep-submicrometer MOSFET’s,” IEEE Electron Device Lett., vol. 11, no. 2, pp. 90−92, Feb. 1990.
[4.8] T. Wang, T.-E. Chang, L.-P. Chiang, C.-H. Wang, N.-K. Zous, and C. Huang, “Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique,” IEEE Trans. Electron Devices, vol. 45, no. 7, pp. 1511−1517, Jul. 1998.
[4.9] N. K. Zous, M. Y. Lee, W. J. Tsai, A. Kou, L. T. Huang, T. C. Lu, C. J. Liu, T. Wang, W. P. Lu, W. Ting, J. Ku, and C.-Y. Lu, “Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 649−651, Sept. 2004.
[4.10] P. Restle, “Individual oxide traps as probes into submicron devices,” Appl. Phys. Lett., vol. 53, no. 19, pp. 1862−1864, Nov. 1988.
[4.11] M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: a new perspective on individual defects, interface states, and low-frequency noise,” Adv. Phys., vol. 38, no. 4, pp. 367−468, 1989.
[4.12] ISE TCAD Manual Release 10.0, Integr. Syst. Eng., Zurich, Switzerland, 2004.
[4.13] Y. Roizin and V. Gritsenko, “ONO structures and oxynitrides in modern microelectronics: material science, characterization and application,” in Dielectric Films for Advanced Microelectronics, M. Baklanov, K. Maex, and M. Green, Ed. Chichester, U.K.: Wiley, 2007, pp. 251−295.
[4.14] Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, “Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 540−542, Nov. 2000.
[4.15] A. V. Shaposhnikov, I. P. Petrov, V. A. Gritsenko, and C. W. Kim, “Electronic band structure and effective masses of electrons and holes in the  and  phases of silicon nitride,” Phys. Solid State, vol. 49, no. 9, pp. 1628−1632, Sep. 2007.
[4.16] E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, N. Akil, M. J. van Duuren, and D. S. Golubovć, “Experimental and simulation analysis of program/retention transients in silicon nitride-based NVM cells,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1980−1990, Sep. 2009.
[4.17] İ. Ay, and H. Tolunay, “Steady-state and transient photoconductivity in hydrogenated amorphous silicon nitride films,” Sol. Energy Mater. Sol. Cells, vol. 80, pp. 209−216, 2003.
[4.18] A. Padovani, A. Arreghini, L. Vandelli, L. Larcher, G. Van den bosch, P. Pavan, and J. Van Houdt, “A comprehensive understanding of the erase of TANOS memories through charge separation experiments and simulations,” IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3147−3155, Sep. 2011.

Chapter 5

[5.1] H.-J. Kang, N. Choi, S.-M. Joe, J.-H. Seo, E. Choi, S.-K. Park, B.-G. Park, and J.-H. Lee, “Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure,” in VLSI Symp. Tech. Dig., 2015, pp. T182−T183.
[5.2] B. Choi, S. H. Jang, J. Yoon, J. Lee, M. Jeon, Y. Lee, J. Han, J. Lee, D. M. Kim, D. H. Kim, C. Lim, S. Park, and S.-J. Choi, “Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory,” in VLSI Symp. Tech. Dig., 2016, pp. 78−79.
[5.3] K. Mizoguchi, S. Kotaki, Y. Deguchi, and K. Takeuchi, “Lateral charge migration suppression of 3D-NAND flash by VTH nearing for near data computing,” in IEDM Tech. Dig., 2017, pp. 465−468.
[5.4] W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, T. Wang, S. Pan, and C.-Y. Lu, “Cause of data retention loss in a nitride-based localized trapping storage flash memory cell,” in Proc. IEEE Int. Rel. Phys. Symp., 2002, pp. 34−38.
[5.5] Y. Roizin and V. Gritsenko, “ONO structures and oxynitrides in modern microelectronics: material science, characterization and application,” in Dielectric Films for Advanced Microelectronics, M. Baklanov, K. Maex, and M. Green, Ed. Chichester, U.K.: Wiley, 2007, pp. 251−295.
[5.6] A. Maconi, A. Arreghini, C. Monzio Compagnoni, G. Van den bosch, A. S. Spinelli, J. Van Houdt, and A. L. Lacaita, “Impact of lateral charge migration on the retention performance of planar and 3D SONOS devices,” in Proc. European Solid-State Device Research Conf., 2011, pp. 195−198.
[5.7] A. Maconi, A. Arreghini, C. Monzio Compagnoni, G. Van den bosch, A. S. Spinelli, J. Van Houdt, and A. L. Lacaita, “Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices,” Solid State Electron., vol. 74, no. 8, pp. 64−70, Aug. 2012.
[5.8] D. Fuks, A. Kiv, Y. Roizin, M. Gutman, R. Avichail-Bibi, and T. Maximova, “The nature of HT Vt shift in NROM memory transistors,” IEEE Trans. Electron Devices, vol. 53, no. 2, pp. 304−313, Feb. 2006.
[5.9] C. Kang, J. Choi, J. Sim, C. Lee, Y. Shin, J. Park, J. Sel, S. Jeon, Y. Park, and K. Kim, “Effects of lateral charge spreading on the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory,” in Proc. IEEE Int. Rel. Phys. Symp., 2007, pp. 167–170.
[5.10] L. Liu, A. Arreghini, G. Van den bosch, L. Pan, and J. Van Houdt, “Assessment methodology of the lateral migration component in data retention of 3D SONOS memories,” Microelectronics reliability, vol. 54, no. 9−10, pp. 1697−1701, Aug. 2014.
[5.11] Y. H. Liu, H. Y. Lin, C. M. Jiang, T. Wang, W. J. Tsai, T. C. Lu, K. C. Chen, and C.-Y. Lu, “Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method,” in Proc. IEEE Int. Rel. Phys. Symp., 2018, pp. 6D.1-1–6D.1-5.
[5.12] Y.-H. Liu, T.-C. Zhan, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Investigation of electron and hole lateral migration in silicon nitride and data pattern effects on Vt retention loss in a multi-level charge trap flash memory,” to be published in IEEE Trans. Electron Devices, 2019.
[5.13] Y.-H. Liu, C.-M. Jiang, H.-Y. Lin, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method,” Appl. Phys. Lett., vol. 111, no. 3, p. 033501, Jul. 2017.
[5.14] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, ”Random telegraph noise of deep-submicrometer MOSFET’s,” IEEE Electron Device Lett., vol. 11, no. 2, pp. 90−92, Feb. 1990.
[5.15] Y.-H. Liu, C.-M. Jiang, W.-C. Chen, T. Wang, W.-J. Tsai, T.-C. Lu, K.-C. Chen, and C.-Y. Lu, “Electric field induced nitride trapped charge lateral migration in a SONOS flash memory,” IEEE Electron Device Lett., vol. 38, no. 1, pp. 48−51, Jan. 2017.
[5.16] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C.-Y. Lu, and S. H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” in IEDM Tech. Dig., 2001, pp. 719−722.
[5.17] H.-C. Ma, Y.-L. Chou, J.-P. Chiu, Y.-T. Chung, T.-Y. Lin, T. Wang, Y.-P. Chao, K.-C. Chen, and C.-Y. Lu, “A novel random telegraph signal method to study program/erase charge lateral spread and retention loss in a SONOS flash memory,” IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 623−630, Mar. 2011.
[5.18] ISE TCAD Manual Release 10.0, Integr. Syst. Eng., Zurich, Switzerland, 2004.
[5.19] N. K. Zous, M. Y. Lee, W. J. Tsai, A. Kou, L. T. Huang, T. C. Lu, C. J. Liu, T. Wang, W. P. Lu, W. Ting, J. Ku, and C.-Y. Lu, “Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 649−651, Sept. 2004.