臺灣博碩士論文加值系統

本文運用調變氮化矽緩衝薄膜的緻密度，將形成「鍺量子點/二氧化矽/矽鍺殼層」異質結構構之製程溫度降至850°C。此外，我們可以透過鍺間隙原子的催化，大幅降低緻密化以及氧化氮化矽的製程溫度至750°C。
過去的製程是在900°C濕氧下，形成「鍺量子點/二氧化矽/矽鍺殼層」的異質結構。然而，現今的CMOS製程溫度都低於900°C。為了使鍺量子點異質結構的製程溫度可以與現今的CMOS製程匹配，本文藉由調變氮化矽緩衝薄膜的緻密度，成功在850°C濕氧，形成「鍺量子點/二氧化矽/矽鍺殼層」的異質結構。另外，我們在750900°C濕氧的過程中，觀察到鍺間隙原子會催化鄰近的氮化矽分解、緻密化甚至氧化，對於先進的CMOS製程以及光子應用方面有很大的進展。

In this thesis, we have reduced the process temperature of Ge QD/SiO2/SiGe shell heterostructure to 850°C by changing the density of silicon nitride. In addition, we discover the process temperature of densification and oxidation of silicon nitride layers could be reduced to 750°C by mediating exquisite Ge interstitials in close proximity.
The previously process of Ge QD/SiO2/SiGe shell heterostructure is under 900°C in an H2O ambient. However, the process temperature of advanced CMOS is below 900°C. In this thesis, we have fabricated Ge QD/SiO2/SiGe shell heterostructure at 850°C by changing the density of silicon nitride. Besides, we have observed that Ge interstitials would catalyze the decomposition, densification, and even oxidation of silicon nitride during thermal oxidation process under temperature range between 750900°C in an H2O ambient. The Ge-mediated densification and oxidation of silicon nitride have strong implications for advanced CMOS electronics and photonics applications.

摘要 I
Abstract II
目錄 IV
圖目錄 VI
表目錄 XII
第一章 簡介與研究動機 1
1-1簡介 1
1-2 鍺金氧半場效電晶體之介面工程 2
1-3 現今CMOS製程之熱預算 3
1-4 研究動機 4
1-5 論文架構 5
第二章 氧化溫度對於鍺量子點的形成、熟化和移動之影響 10
2-1前言 10
2-2實驗結構製作 12
2-3 鍺間隙原子催化氮化矽之分解與氧化對氧化溫度的相依性 13
第三章 鍺間隙原子在中溫區段催化氮化矽緻密化以及氧化之機制探討 23
3-1 前言 23
3-2鍺間隙原子於750900oC催化氮化矽緻密化之實驗設計 24
3-2-1 鍺間隙原子於900oC催化Si3N4緻密化之回顧 24
3-2-2 實驗觀察鍺間隙原子於800850oC催化SixNy:H之緻密化 25
3-2-3 實驗觀察鍺間隙原子於750oC催化Si3N4之緻密化 27
3-3鍺間隙原子催化氮化矽緻密化與氧化之機制 29
第四章 矽鍺柱幾何尺寸與氮化矽效應對於鍺量子點的形成和移動之影響 39
4-1前言 39
4-2矽鍺合金之幾何形狀或是面積效應 39
4-2-1多晶矽鍺連續薄膜與多晶矽鍺奈米柱之差異 39
4-2-2多晶矽鍺奈米柱之尺寸效應 40
4-3 LPCVD與PECVD的氮化矽對於鍺量子點的形成、移動之影響 42
第五章、總結與未來展望 47
參考文獻 48
Vita 54

[1] S. Takagi et al., "Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance," IEEE Trans. Electron Devices, vol. 55, no.1, p. 25, 2008.
[2] K. Kuhn et al., "Past, present and future: SiGe and CMOS transistor scaling," Electrochemical society trans., vol. 33, no. 6, pp. 13-17, 2010.
[3] E.P. Gusev, Huiling Shang, Matt Copel, M.A. Gribelyuk, C. D’Emic, P. Kozlowski, T. Zabel, "Microstructure and thermal stability of HfO2 gate dielectric deposited on Ge (100)," Appl. Phys. Lett., vol. 85, no. 12, pp. 2334-2336, 2004.
[4] T. Ghani et al., "A 90-nm high volume manufacturing logic technology featuring novel 45-nm gate length strained silicon CMOS transistors," IEDM Tech. Dig., pp. 978–980, 2003.
[5] T. Maeda, M. Nishizawa, and Y. Morita, "Role of germanium nitride interfacial layers in HfO2 /germanium nitride/germanium metal–insulator– semiconductor structures," Appl. Phys. Lett., vol. 90, pp. 072911-1-072911-3, 2007.
[6] Ruilong Xie and Chunxiang Zhu, "Effects of sulfur passivation on Germanium MOS Capacitors with HfON Gate Dielectric," IEEE Electron Device Letters, vol. 28, no. 11, pp. 976-979, 2007.
[7] W. P. Bai, N. Lu, and D.-L. Kwong, "Si interlayer passivation on germanium MOS capacitors with high-dielectric and metal gate," IEEE Electron Device Letters, vol. 26, no. 6, 2005.
[8] Martin M. Frank, Steven J. Koester, Matthew Copel, John A. Ott, Vamsi K. Paruchuri, and Huiling Shang, "Hafnium oxide gate dielectrics on sulfur-passivated germanium," Appl. Phys. Lett., vol. 89, pp. 112905-1-112905-3, 2006.
[9] G. Venkata Rao, M.Kumar, T.V.Rajesh, D.V. Rama Koti Reddy, D.Anjaneyulu, B. Sainath and S.V.Jagadeesh Chandra, "Investigations on the nitride interface engineering at HfO2/Ge stacks for MOS devices," Materials Today: Proceedings, vol. 5, no. 1, pp. 650-656, 2018.
[10] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, "Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces," Appl. Phys. Lett., vol. 76, no.16, pp. 2244-2246, 2000.
[11] A. P. Huang, Z. C. Yang, and P. K. Chu, "Hafnium-based high-k gate dielectrics," Advances in solid state circuit technologie, pp.333-350, 2010.
[12] A.Vandooren et al., "Key challenges and opportunities for 3D sequential integration," IEEE, 2018
[13] N. Usami, T. Mine, S. Fukatsu, and Y. Shiraki, "Realization of crescent‐shaped SiGe quantum wire structures on a V‐groove patterned Si substrate by gas‐source Si molecular beam epitaxy," Appl. Phys. Lett., vol. 63, no. 20, p. 2789, 1993.
[14] K. Kawaguchi, N. Usami, Y. Shiraki, "Formation of Ge QD/SiO2/SiGe heterostructure formed at medium temperatures," Thin Solid Films, vol. 369, p. 126, 2000.
[15] C. Fenouillet-Beranger et al., "FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration," Solid State Electronics, vol. 113, pp. 2-8, 2015.
[16] P Batude et.al., "3DVLSI with CoolCube process: An alternative Path to Scaling," VLSI-T, pp. T48-T49, 2015.
[17] C. M.V Lu et al., "Key process steps for high performance and reliable 3D sequential integration," VLSI, 2017.
[18] P. Batude et al., "3D sequential integration opportunities and technology optimization," IEEE Int. Interconnect Technol. Conf., pp. 373–376, 2014.
[19] P. Batude et al., "3D Sequential Integration: Application-Driven technological achievements and guidelines," IEEE International Electron Devices Meeting, pp. 52-55, 2017.
[20] W. T. Lai, K. C. Yang, P. H. Liao, T. George and P. W. Li, "Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors," Frontiers in Materials, vol.3, Article 5, 2016.
[21] C. Wagner, "Oxidation of alloys involving noble metals," J. Electrochem. Soc., vol. 103, pp. 571-580, 1956.
[22] D. Starodub, E. P. Gusev, E. Garfunkel and T. Gustafsson, "Silicon oxide decomposition and desorption during the thermal oxidation of silicon," Surf. Rev. Lett., vol. 6, no. 1, pp. 45–52, 1999.
[23] A. Stekolnikov and F. Bechstedt, "Shape of free and constrained group-IV crystallites: Influence of surface energies," Physical Review B, vol. 72, no. 12, p. 125326, 2005.
[24] M. H. Kuo, M. M. Lee, and P.W. Li, " High photoresponsivity germanium nanodot photo-MOSFETs for monolithically-integrated Si optical interconnects," IEEE Electron Devices Technology and Manufacturing Conference Proceedings of Technical Papers, pp. 189–190, 2017.
[25] M. H. Kuo, P. Y. Hong, P. C. Liu, M. C. Lee, H. C. Lin, T. George, and P. W. Li, "Very large photoresponsiviy and high photocurrent linearity for Ge-dot/SiO2/SiGe photoMOSFETs under gate modulation," Optics Express, vol. 25, no. 21, pp. 25467–25476, 2017.
[26] K. H. Chen, C. C. Wang, T. George, and P. W. Li, "The pivotal role of SiO formation in the migration and Ostwald ripening of Ge quantum dots," Appl. Phys. Lett., vol. 105, p. 122102, 2014.
[27] L. Nesbit, "Annealing characteristics of Si‐rich SiO2 films," Appl. Phys. Lett., vol. 46, no. 1, pp. 38-40, 1985.
[28] M. J. Shaw, J. Guo, G. A. Vawter, S. Habermehl, and C. T. Sullivan, "Fabrication techniques for low-loss silicon nitride waveguides," in Proc. Micromachining Technol. Micro-Opt. Nano-Opt. III, vol. 5720, pp. 109-118, 2005.
[29] J. F. Bauters, M. J. R. Heck, D. D. John, J. S. Barton, C. M. Bruinink, A. Leinse, R. G. Heideman, D. J. Blumenthal, and J. E. Bowers, "Planar waveguides with less than 0.1 dB/m propagation loss fabricated with wafer bonding," Opt. Express, vol. 19, p. 24090 2011.
[30] K. P. Peng, T. L. Huang, T. George, H. C. Lin and P. W. Li, "Ge nanodot-mediated densification and crystallization of low-pressure chemical vapor deposited Si3N4 for advanced complementary metal-oxide-semiconductor photonics and electronics applications," Nanotechnology, vol. 30, 405201, 2019.
[31] Y. R. Luo, "Bond dissociation energies," in CRC Handbook of Chemistry and Physics, 90th ed., 2009.
[32] J. Plummer, M. D. Deal, P. B. Griffin, “Silicon VLSI technology； fundamentals, practice and modeling,” Prentice Hall Electronics and VLSI series, p. 349, 2000.
[33] C. C. Wang, P. H. Liao, M. H. Kuo, T. George and P. W. Li, "The curious case of exploding quantum dots:anomalous migration and growth behaviors of Ge under Si oxidation," Nanoscale Research Letters, vol. 8, no. 192, p. 4, 2013.
[34] K. H. Chen, C. C. Wang, T. George, and P. W. Li, “The pivotal role of SiO formation in the migration and Ostwald ripening of Ge quantum dots” Appl. Phys. Lett., vol. 105, p. 122102, 2014.