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研究生:陳博恩
研究生(外文):Chen, Bo-En
論文名稱:在可程式化邏輯閘陣列上用於查詢加速的可重新配置的資料庫處理器
論文名稱(外文):Reconfigurable Database Processor for Query Acceleration on FPGA
指導教授:賴伯承
指導教授(外文):Lai, Bo-Cheng
口試委員:張添烜張錫嘉賴伯承
口試委員(外文):Chang, Tian-SheuanChang, Hsie-ChiaLai, Bo-Cheng
口試日期:2020-07-16
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:41
中文關鍵詞:查詢加速資料庫處理可程式化邏輯閘陣列
外文關鍵詞:Query accelerationDatabase processingFPGA
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感測技術和網路的進步使得產生大數據成為可能,資料庫成為了支援搜尋和分析資料重要的儲存空間。隨著感測技術和網路的進步,大量的資料在資料庫中被產生和收集。急劇增加的資料量使得及時回應查詢要求成為一個巨大的挑戰。為了支援現今資料庫所需的高運算吞吐量,FPGA(場域可程式化邏輯閘陣列)被用來作為實現高吞吐量的資料庫查詢功能的高效加速平台。然而,和其他的可程式化處理器相比,FPGA繁瑣且耗時的設計流程是一個沉重的設計考量。以往FPGA上的加速器選擇資料庫一系列查詢操作中單一的運算(例如排序)來做加速。而寫死固定的硬體設計也使得FPGA對於支援不同查詢和操作上較沒有彈性。本篇論文提出一個可重新配置的加速器架構來支援端對端的查詢加速。我們提出針對不同資料處理操作的模組化的引擎,這個引擎可以針對不同的設計參數重新配置。資料處理模組按照不同運算階段分配,並且針對查詢要求組成並產生加速器架構。透過我們的系統化解決方案,FPGA上的加速器可以適應不同的查詢要求。透過TPC-DS的實驗,我們提出的架構比傳統的CPU解決方案快56.5%。和前人的FPGA設計相比,提出的加速器在總體性能上快23.8%,節省50.09% FPGA的資源使用。我們的實驗也顯示和固定設計相比,可重新配置的設計可以更有效率的適應不同查詢特徵並獲得30.1%的性能提升
Database has become an important repository to support search and analysis of a dataset. With the advances of sensing and networking technology, vast amount of data is being generated and collected in databases. The drastically growing volume of database has made the in-time query response a great challenge. To support the excessive processing throughput required by the modern big database, FPGA (Field Programmable Gate Array) has been adopted as an efficient acceleration platform to attain high throughput database queries. However, when compared with programmable processors, the cumbersome and time-consuming design process of FPGA becomes a serious design concern. Previous accelerators on FPGA chose to support only the single operator, such as sorting, along the series of operations in a database query. The hard-coded hardware design also makes FPGA inflexible to support different queries and operations. This thesis proposes a Reconfigurable Database Processor (RDP) to support end-to-end query acceleration. We introduce the modular engines for different data processing operations in queries. The engines can be reconfigured to support different design parameters. The data processing modules are allocated into stages, and composed to generated the accelerator structure for queries. RDP can be adapted to the requirements of different queries by applying our systematic solution. The experiments on the queries of TPC-DS, the proposed RDP has attained 56.5% over the conventional solution on CPU. When compared with the previous FPGA designs, RDP shows 23.8% advantage on the overall performance while saving 50.09% FPGA resources. We have also shown that the reconfigurable designs can more effectively adapt to the query characteristics and attain up to 30.1% performance gain when compared with a fixed design.
摘要 I
ABSTRACT II
誌謝 IV
Contents V
List of Figures VII
List of Tables VII
Chapter 1 Introduction 1
Chapter 2 Background and Related Works 6
2.1 Overview of query processing 6
2.2 Selection Stage 9
2.3 Join Stage 10
2.4 Aggregation Stage 12
2.5 Sorting Stage 13
2.6 Summary of Different Stages 14
Chapter 3 System architecture of Query Accelerator 15
3.1 Data Flow in TPC-DS Query 15
3.2 Overall Architecture 16
3.3 Controller 18
3.4 Comparator 19
3.5 Sorter 19
3.6 Selection Engine 21
3.7 Join Engine 23
3.8 Reconfigurable with Different Types of Queries 25
Chapter 4 Experimental Results 28
4.1 Simulation Model 28
4.2 SystemC Model 28
4.3 TPC-DS benchmark 29
4.4 Performance Comparison Between Different Accelerator 29
4.5 Resource Comparison Between Different Accelerator 32
4.6 Performance Comparison Between Different Queries 33
4.7 Support Reconfigurable Architecture 34
Chapter 5 Conclusions 36
References 37
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