臺灣博碩士論文加值系統

隨著半導體製程的設計規則(Design rule)的不斷降低，關鍵層的覆蓋誤差(Overlay error)控制變得越來越重要和具有挑戰性，光罩的熱效應是造成覆蓋誤差的主要因素，近年來，陸續有提出用於光罩熱效應控制的想法和技術，並認為可以降低光罩熱效應。當深紫外光(Deep-Ultraviolet light)照射到光罩時，大部分的光線會穿過Quatz玻璃基板，一小部分將被反射回去，其餘的部分將被吸收到光罩材料中，尤其是鉻(Chrome)膜吸收熱能，光罩吸收熱能後產生膨脹，導致微影製程的覆蓋誤差，其中又以Shot Scaling (晶粒本層圖形相對前層圖形向外擴張)更是顯著。
　　本文以曝光量為主要影響因此，並通過實驗研究其影響。使用各種曝光量於晶圓上，比較覆蓋誤差的量測值。結果發現，即使在低曝光量的情況下，也很難避免光罩加熱。且曝光量與覆蓋誤差量測值呈現線性關係。本研究將使用熱模擬分析軟體Ansys Icepak來模擬各種曝光量的光罩受熱時溫度分布、形變分析。再利用高階補償來驗證覆蓋誤差可以被有效控制。

As the design rules of semiconductor processes continue to decrease, the control of overlay error of critical layers becomes more and more important and challenging. The thermal effect of photomasks is the main factor that causes overlay errors. , Have successively proposed ideas and techniques for controlling the thermal effect of the photomask, and believe that the thermal effect of the photomask can be reduced. When deep ultraviolet light (Deep-Ultraviolet light) shines on the photomask, most of the light will pass through the Quatz glass substrate, a small part will be reflected back, and the rest will be absorbed into the photomask material, especially chromium (Chrome) The film absorbs thermal energy, and the photomask expands after absorbing the thermal energy, resulting in coverage errors of the lithography process. Among them, Shot Scaling (the grains of the current layer of the grain expand outward relative to the front layer) is more significant.
　　 This article takes exposure as the main influence. Therefore, the influence is studied through experiments. Use various exposures on the wafer to compare the measurement values of the coverage error. As a result, it was found that even in the case of low exposure, it is difficult to avoid heating of the photomask. And the exposure amount and the measurement value of the coverage error have a linear relationship. In this study, the thermal simulation analysis software Ansys Icepak will be used to simulate the temperature distribution and deformation analysis of various exposure masks when heated. Then use high-order compensation to verify that the coverage error can be effectively controlled.

摘要 i
第一章 1
1-1 前言 1
1-2 研究動機 1
1-3 文獻回顧 2
第二章 半導體製程及覆蓋誤差介紹 4
2-1 半導體製程簡介 4
2-2 微影製程簡介 5
2-3 微影製程機台及對準流程 13
2-3-1 步進式軌道機(Track) 13
2-3-2 曝光機 14
2-3-3 對準流程介紹 14
2-4 光罩製作及光罩熱效應介紹 15
2-5 微影製程覆蓋誤差介紹 16
2-6 熱模擬軟體(Ansys Icepak)簡介及流程 19
2-7 高階補償簡介 19
第三章 實驗方法與實驗設計 26
3-1 實驗方法 26
3-2 實驗設計 26
3-3 實驗計畫流程圖 27
3-4 實驗儀器：光阻塗佈機、曝光機、覆蓋誤差量測機 29
3-5 Icepak條件設定與模擬數據 32
第四章 實驗結果分析 45
4-1 實驗分析重點與方法 45
4-2 實驗結果分析 45
第五章 結論與未來展望 49
5-1結論 49
5-2未來展望 50

[1] D. S. Perioff，“A Four-Point Electrical Measurement Technique for Characterizing Mask Superposition Errors on Semiconductor Wafer”，“IEEE Journal of Solid-State Circuits”, vol.SC-13, no.4, pp.436-444, Aug.1978.
[2] Z-C. LIN and W.-J. WU，“Multiple Linear Regression Analysis of the Overlay Accuracy Model”，“IEEE Transactions on Semiconductor Manufacturing”, vol.12,no.2, pp.229-237, May.1999.
[3] C. Gould ， “Advanced Process Control : Basic Functionality Requirements for Lithography”，“IEEE/SEMI Advanced Semiconductor Manufacturing Conference”, pp.49-53, April 2001.
[4] C. Gould ， “Advanced Process Control : Benefits For Photolithography Process Control”，“IEEE/SEMI Advanced Semiconductor Manufacturing Conference”,pp.49-53, April 2002.
[5] C. C. Fu，G. Seligman and P. Tapp，“Implementation and benefits of advanced process control for lithography CD and Overlay Proceedings of SPIE” , vol.5038, pp.362-372, 2003.
[6] C. A. Bode，B. S. Ko，and T. F. Edgar，“Run-to-Run Control and performance monitoring of overlay in semiconductor manufacturing”, Control Engineering Practice, vol. 12, pp.893-900, 2004.
[7] S. J. Park，M. S. Lee，S. Y. Shin，K. H. Cho，J. T. Lim，B. S. Cho，Y. H. Jei，M. K. kim and C. H. Park，“Run-to-Run Overlay Control of Steppers in Semiconductor Manufacture Systems Based on History Data Analysis and Neural Network Modeling”，“IEEE Transactions on Semiconductor Manufacturing”, vol 18, no.4, pp.605-613, Nov 2005.
[8] S. K. Firth，W. J. Campbell，A.Toprac，and T. F. Edgar，“Just-in-Time Adaptive Disturbance Estimation for Run-to-Run Control of Semiconductor Processes”，“IEEE Transactions on Semiconductor Manufacturing”, vol 19, no.3, pp.298-315, Aug 2006.
[9] 莊達仁，“VLSI 製造技術”，高立圖書有限公司著作發行，2002。
[10] Quirk. Serda 著“半導體製造技術”，滄海書局，2003。
[11] PSC Training 教材“Overlay Basic”，2004。
[12] PSC Training 教材“Canon ES6a Alignment System”，2006。